Self-calibrating on-chip interconnects
Abstract/Contents
- Abstract
- This dissertation covers the conception, design and evaluation of the self-calibrating interconnect, a new type of capacitively-driven on-chip interconnect that uses feedback and charge-pumps to automatically neutralize receiver offsets caused by device mismatch. It can operate with extremely low signal swings, which minimizes energy, without compromising reliability. A 2 mm long prototype built in a 90 nm low-power CMOS process consumes 77 fJ/bit of energy at 1.5 GHz, and sustains a bit-error rate (BER) below 10^-30 with just 32 mV of swing. We also present a new way to reduce the noise level of comparators by adjusting the size of the precharge devices. For a given energy budget, we demonstrate that by upsizing the precharge devices we can reduce the input-referred thermal noise of the popular StrongARM latch by up to 30% over previously known sizing techniques.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Chen, James |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Dally, William |
| Primary advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Dally, William |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Advisor | Wooley, Bruce A, 1943- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | James Chen. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Ph.D. Stanford University 2012 |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by James Chen
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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