The impact of III-V and GE devices on circuit performance
Abstract/Contents
- Abstract
- Because the performance enhancement from scaling in accordance to Moore's law encounters difficulties, recent research has focused on finding new device materials with higher intrinsic carrier mobility. III-V and Ge MOSFETs have been, especially, studied as potential replacements for Si MOSFETs. This dissertation addresses the building of spice-compatible models for such new devices, the estimation of the delay and energy of digital circuits, and the performance comparison of various digital blocks and SRAM cells with different combinations of Si, III-V, and Ge devices. This work, first, develops spice-compatible III-V nFET and Ge pFET models in order to estimate the actual gain of using these devices in digital circuits. A compact model is employed for modeling the III-V nFET, a modified BSIM library is used for describing the Ge pFET, and a RC model is adopted for counting the effect of wires. With these models, various common digital blocks are explored. This thesis covers the modeling and simulations of the delay and energy of digital logics, including inverters, 32-bit adders, interconnect drivers as well as FPGAs. The driving capability of the nFET and pFET should be matched for optimum noise margin and performance, in typical digital design. Both capacitance and driving current are important for performance. The combination of III-V nFET with a thick barrier layer and Ge pFET achieves the best delay-energy performance for many digital logic circuits. The advantages of small capacitance and high driving capability disappear with long wire interconnect. FPGA design does not benefit from advanced device because the delay-energy performance is dominant by wires. An SRAM cell is also studied. This work addresses the trade-offs between performance specifications including noise tolerance of SRAM cells comprising Si, III-V, and Ge device. The read margin of SRAM is maximized with the Si passgate, the III-V nFET pull-down, and the Ge pFET pull-up transistor. The write margin of SRAM, on the other hand, is maximized with the III-V passgate, III-V nFET pull-down, and Ge pFET pull-up transistor. There is a tradeoff between read and write margin. The modeling and simulation methodology and insights provided in this thesis enable us to determine the actual gain of digital circuits with advanced devices. The results offer suggestions for the direction of future device development.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Park, Jeongha |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wong, S |
| Thesis advisor | Wong, S |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Mitra, Subhasish |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Jeongha Park. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Jeongha Park
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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