Monolithic three-dimensional integration of carbon nanotube digital VLSI
Abstract/Contents
- Abstract
- Today's two-dimensional integrated circuits (2D ICs) generally consist of a single layer of transistors and multiple layers of interconnects that are integrated vertically using inter-layer vias (ILVs). In contrast, three-dimensional ICs (3D ICs) consist of two or more layers of transistors (and multiple interconnect layers) that are integrated vertically using ILVs. For 3D ICs to achieve high energy-efficiency and small form factor, high-density ILVs, such as conventional vias used in today's 2D ICs, are preferred. Monolithic 3D integration can achieve this objective through sequential integration of multiple layers of circuits on a single wafer. However, monolithic 3D integration is difficult because the circuits on the upper layers of monolithic 3D ICs must be fabricated at temperatures below 400 °C; otherwise, the circuits on the lower layers can degrade. Carbon Nanotube Field-Effect Transistors (CNFETs) offer a unique opportunity to achieve monolithic 3D integration. This is because the high-temperature Carbon Nanotube (CNT) growth can be decoupled from CNFET circuit fabrication process through a low-temperature (130°C) CNT transfer technique. Moreover, CNFETs are excellent candidates for building highly energy-efficient digital systems of the future. Unfortunately, CNTs are subject to substantial inherent imperfections resulting from mis-positioned CNTs and metallic CNTs. In this dissertation, we experimentally demonstrate, for the first time, monolithic 3D ICs using CNFETs with the following features: 1. Scalable monolithic 3D integration of CNFET circuits that are immune to mis-positioned CNTs and metallic CNTs. 2. Flexible monolithic 3D integration where complementary CNFETs can be placed on arbitrary layers of monolithic 3D ICs and connected using conventional vias to build monolithic 3D logic circuits. 3. Functional CNFET monolithic 3D circuits operating using supply voltages from 3V down to sub-0.4V, with a fully-complementary CNFET inverter operating at 0.2V. Such CNFET monolithic 3D ICs, together with ultra-low voltage operation, create exciting opportunities for high-performance and highly energy-efficient digital system design.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Wei, Hai |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, S. Simon |
| Advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Wong, S. Simon |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Hai Wei. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Hai Wei
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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