Improving energy efficiency for CGRA architectures

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The rise of edge computing has resulted in a growing need for executing computationally intensive tasks within strict energy constraints. ASICs are typically used to achieve high performance and energy efficiency, but at the expense of hardware flexibility. Given the fast-paced evolution of edge applications, there is a pressing requirement for flexible yet energy-efficient architectures that can keep up with the latest trends. Traditionally, reconfigurable computing devices have used processors, where instructions configure the processor in each clock cycle to perform the desired operation. More recently, researchers have explored using Field Programmable Gate Arrays (FPGA), and Coarse-Grained Reconfigurable Architectures (CGRA), which configure the hardware in space (and not time) to provide programmable computing devices. In the space of spatial programmable architectures, CGRAs are a promising alternative to FPGAs due to their higher energy efficiency that comes from operating at a word-level granularity in logic and routing. This thesis introduces two methods to improve the energy efficiency of CGRAs. First, low-access-cost distributed memories are introduced into the processing elements. While similar to conventional register files, these memories are optimized to work with applications with streaming data, so they "push" the data to the computing elements. These memories help improve the energy efficiency of Deep Neural Network (DNN) applications on the CGRAs. The second method aims to improve the energy efficiency of CGRAs by introducing low-overhead fine-grained power domains to better optimize both active and idle power. Both these techniques have been integrated into a taped out SoC with a CGRA optimized for Deep Learning and Computer Vision applications.


Type of resource text
Form electronic resource; remote; computer; online resource
Extent 1 online resource.
Place California
Place [Stanford, California]
Publisher [Stanford University]
Copyright date 2023; ©2023
Publication date 2023; 2023
Issuance monographic
Language English


Author Nayak, Ankita
Degree supervisor Horowitz, Mark (Mark Alan)
Thesis advisor Horowitz, Mark (Mark Alan)
Thesis advisor Hanrahan, P. M. (Patrick Matthew)
Thesis advisor Raina, Priyanka, (Assistant Professor of Electrical Engineering)
Degree committee member Hanrahan, P. M. (Patrick Matthew)
Degree committee member Raina, Priyanka, (Assistant Professor of Electrical Engineering)
Associated with Stanford University, School of Engineering
Associated with Stanford University, Department of Electrical Engineering


Genre Theses
Genre Text

Bibliographic information

Statement of responsibility Ankita Nayak.
Note Submitted to the Department of Electrical Engineering.
Thesis Thesis Ph.D. Stanford University 2023.

Access conditions

© 2023 by Ankita Nayak
This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).

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