Design of low power image sensor for computational photography
Abstract/Contents
- Abstract
- This research investigates the design of the peripheral circuits of a CMOS image sensor in order to determine the minimum energy required to read an image. A novel interleaved readout architecture with partial settling is proposed and implemented. Unlike prior designs, this image sensor removes the need for a high-bandwidth gain stage that consumes a large amount of static power. We use a successive approximation register analog-to-digital converter (SAR ADC), pulse the current used to settle the imager bitlines, and minimize this current by only partially settling the SAR input capacitance to the bitline voltage. The residual systematic error is removed in the digital domain. Gain adjustment can be accomplished by varying the floating diffusion capacitance CFD inside pixels. In addition, instead of reading out all the columns simultaneously through the conventional ADC-per-column architecture, which has a very poor routing efficiency with pixel scaling, we share multiple columns to a single ADC and read them sequentially within a row time. Thus, the proposed image sensor accomplishes both high power efficiency and fast readout speed. A 320Hx240V prototype sensor with two column-shared 10-bit synchronous SAR-ADCs is implemented with 180nm technology, which consumes 1.46mW operating at 130fps. The figure of merit (FOM) computed in terms of energy consumed at each pixel per frame is 146pJ/pixel/frame. This number is about 5 times smaller than prior designs. The performance of the prototype is limited by the ADC quantization noise and finite partial settling attenuation. In addition, the synchronous SAR ADC dissipates a large amount of power at the conversion clock tree distribution. A few additional optimizations can address these issues and achieve an image sensor with a FOM of 102pJ/pixel/frame.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2016 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Ji, Suyao |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Horowitz, Mark |
| Thesis advisor | Horowitz, Mark |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Advisor | Murmann, Boris |
| Advisor | Wooley, Bruce A, 1943- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Suyao Ji. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2016. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2016 by Suyao Ji
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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