Scaled planar floating-gate NAND flash memory technology : challenges and novel solutions
Abstract/Contents
- Abstract
- NAND flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other portable electronic devices. The NAND flash memory device, consisting of a floating-gate transistor cell, is the most aggressively scaled electronic device, as evidenced by ever-increasing memory capacities. In this work, we will examine possible problems arising from continued scaling of these structures, and discuss novel solutions to overcome them. Firstly, we investigate scaling of the conventional poly-silicon floating-gate, aimed at reducing cell-to-cell interference. We experimentally delineate a new reliability concern for the first time, with programming current through ultra-thin poly-silicon floating-gates becoming increasingly ballistic. We also experimentally demonstrate doping-related issues in the poly-silicon floating-gate. We then apply a novel metal-based floating-gate cell for the first time, designed to overcome the problems discussed above. We explore factors that influence the choice of metal, and demonstrate excellent functionality in ultra-thin metal floating-gate cells scaled down to 3 nm TiN floating-gate thickness, thus greatly reducing cell-to-cell interference. Finally, in order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional silicon oxide-nitride dielectric with high-k dielectric materials. We integrate poly-silicon and metal floating-gate cells with Al2O3 high-k control dielectric. Further, we establish that a deeper work-function control gate is helpful in reducing gate-injection. Combining ultra-thin metal floating-gate, high-k control dielectric and deep work-function control gate, we enable the planar floating-gate cell as a scalable candidate.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Copyright date | 2011 |
| Publication date | 2010, c2011; 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Raghunathan, Shyam Sunder |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Nishi, Yoshio, 1940- |
| Primary advisor | Saraswat, Krishna |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Krishnamohan, Tejas |
| Advisor | Krishnamohan, Tejas |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Shyam Sunder Raghunathan. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Shyam Sunder Raghunathan
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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