Early-life failures in digital logic circuits
Abstract/Contents
- Abstract
- Manufacturing tests detect defective integrated circuits (ICs) before they are shipped to customers. Early-life failures (ELF, also referred to as infant mortality failures) are caused by defective ICs that pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Such failures can hurt the reputation of IC suppliers, and can have consequences ranging from annoying computer crashes, loss of data and services, to financial and productivity losses, or even loss of human life. Major ELF causes include defects in transistor gate dielectrics and inter-metal dielectrics (IMD). Burn-in is traditionally used for ELF screening, where ICs are stressed at elevated voltage and temperature to accelerate defects so that they get detected during manufacturing tests. Burn-in accounts for a significant portion of manufacturing test costs, and there are serious concerns about its potentially reduced effectiveness in advanced technologies. Hence, low-cost burn-in alternatives are necessary. In this dissertation, we make the following contributions: 1. Using test chips over several IC technologies, we derive and experimentally demonstrate a new ELF signature for defects in transistor gate dielectrics: the presence of a gate-dielectric ELF transistor (i.e., a transistor with gate-dielectric defect that may result in ELF) inside a logic gate results in changes in delay of that logic gate over time before functional failures appear. This signature is distinct from gradual delay degradation effects exhibited by several circuit aging mechanisms. 2. We experimentally demonstrate that the ELF signature for IMD defects in advanced IC technologies (e.g., 28nm) is similar to that of transistor gate dielectrics. 3. We experimentally demonstrate that the derived ELF signature can be successfully detected using an on-chip clock control technique. 4. Using an industrial design with 8 processor cores supporting 64 hardware threads, we demonstrate the practicality of automatically generating special test patterns to detect ELF-induced changes in delays. Our results may be used to provide early indications of ELF-induced impending circuit failures during manufacturing tests, or during normal system operation for robust systems with built-in support for on-line self-test, diagnostics, and self-repair.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2013 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Kim, Young Moon |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Advisor | Arbabian, Amin |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Young Moon Kim. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2013 by Young Moon Kim
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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