High-k gate dielectric interfaces with germanium and silicon-germanium substrates
Abstract/Contents
- Abstract
- As transistors scale to their physical limits, germanium and silicon-germanium (SiGe) alloys are both promising candidate metal-oxide-semiconductor field effect transistor (MOSFET) channel materials to extend the roadmap. In this work, I used carefully-controlled atomic layer deposition (ALD) processes and a simple forming gas anneal (FGA), to form TiO2/Al2O3/Ge gate stacks with 0.65 nm EOT and low interface trap densities. For the first time, I applied bilayer gate dielectric stacks to Ge pMOSFETs with sub 1-nm EOT and a subthreshold swing (SS) as low as 71 mV/dec. For the first time, soft x-ray and hard x-ray photoelectron spectroscopy were used to rigorously study the formation of a GeO2 interface layer between an atomic layer deposited gate dielectric and a Ge(100) substrate during forming gas anneal (FGA). A new and simple method was demonstrated to selectively passivate interface traps with energies in the top half of the Ge band gap under annealing conditions that produce a GeO2 interface layer. I also describe how the sensitivity of the interface trap density in metal/Al2O3/Ge MOSCAPs is related to the nature of the H2/N2 anneal and the presence of a gate metal such as Pt that is effective in dissociating H2 to atomic hydrogen. The third part of this work focuses on SiGe substrates. Experiments show that, even though the native oxides of the SiGe channel are removed by 2% HF(aq)/ H2O cyclic cleans, a SiOx/GeOx interfacial layer is formed during Al2O3 ALD. Using Al as the gate metal instead of Pt, Al2O3/SiGe MOSCAPs show C-V curves with minimal frequency dispersion and much smaller Dit response. Experiments reveal that the Al-gate scavenges oxygen from the underlying GeOx, producting a SiOx/SiGe interface with much-reduced Dit.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2016 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Zhang, Liangliang |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | McIntyre, P. (Paul) |
| Thesis advisor | McIntyre, P. (Paul) |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Pianetta, Piero |
| Thesis advisor | Saraswat, Krishna |
| Advisor | Nishi, Yoshio, 1940- |
| Advisor | Pianetta, Piero |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Liangliang Zhang. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2016. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2016 by Liangliang Zhang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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