Antimonide-based III-V CMOS technology
Abstract/Contents
- Abstract
- As scaling of silicon CMOS becomes increasingly difficult, use of alternate materials with high carrier mobilities is being explored extensively. Despite burgeoning interests in III-Vs for realizing high performance transistors at low power, III-V MOSFETs have been plagued by (a) Poor PMOS performance, which makes realizing CMOS in a single material system difficult; (b) Low density of states (DOS) for electrons; (c) Poor surface passivation resulting in high interface trap density; (d) Poor dopant activation in the source-drain (S/D); (e) High contact resistance; (f) Hetero-integration of III-V materials on silicon substrates. This work will present novel solutions to overcome these problems. The design is based on the 0.61-0.62nm lattice constant system with InGaSb as the channel material because of its advantages in terms of band engineering and high mobility/offsets for both electrons and holes. The goal is to achieve high electron/hole mobility in the same channel material for N- and P-channel MOS devices through the optimization of surface passivation, stoichiometry, heterostructure design and novel contact/interface engineering. Hetero-integration on a silicon substrate is another key challenge in enabling III-V CMOS. The hetero-integration scheme for III-V CMOS transistors on silicon using the rapid-melt-growth (RMG) technique is demonstrated.
Description
Type of resource | text |
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Form | electronic; electronic resource; remote |
Extent | 1 online resource. |
Publication date | 2013 |
Issuance | monographic |
Language | English |
Creators/Contributors
Associated with | Yuan, Ze |
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Associated with | Stanford University, Department of Electrical Engineering. |
Primary advisor | Saraswat, Krishna |
Thesis advisor | Saraswat, Krishna |
Thesis advisor | Harris, J. S. (James Stewart), 1942- |
Thesis advisor | Plummer, James L |
Advisor | Harris, J. S. (James Stewart), 1942- |
Advisor | Plummer, James L |
Subjects
Genre | Theses |
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Bibliographic information
Statement of responsibility | Ze Yuan. |
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Note | Submitted to the Department of Electrical Engineering. |
Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
Location | electronic resource |
Access conditions
- Copyright
- © 2013 by Ze Yuan
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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