Block copolymer directed self-assembly for patterning memory and logic
Abstract/Contents
- Abstract
- With the anticipated arrival of high-numerical aperture (NA) extreme ultraviolet (EUV) lithography in the next two years, it is in principle possible to pattern the highest resolution line-space features projected for future semiconductor devices in a single exposure. However, the resolution needed to pattern contact holes past the 3 nm node is still a key challenge in lithography, requiring triple or quadruple patterning with the existing EUV systems or double patterning with the as yet unreleased high-NA EUV systems. Block copolymer directed self-assembly (DSA) is a low-cost, high-throughput patterning technique capable of producing uniform features at the resolution needed beyond the 3 nm node (hole pitch < 25 nm, hole diameter < 20 nm). In this thesis, I will share my work on integrating DSA into fabrication of memory and logic devices. First, I will describe the fabrication process and electrical characterization of a phase change memory (PCM) array patterned using DSA, in which germanium antimony telluride (GST) is confined in 20 nm vias through SiO2. To pattern these vias, a PS-b-PMMA block copolymer was used to shrink an array of 80 nm guides, and the resulting 20 nm DSA patterns were transferred through an amorphous silicon hard mask into SiO2. The PCM devices fabricated were measured to switch at 150-200 µA with a high-resistance state of ~30 MΩ and low-resistance state of ~3 MΩ. When patterning logic, the pattern density variation inherent to contact and via layouts presents an additional challenge from a DSA perspective. That is, for layouts of random logic with non-uniform pattern density, the self-assembly process tends to yield patterns with poor defectivity and uniformity. I will discuss my work on inserting sub-DSA resolution assist features (SDRAFs) features into a via layout to even out its density. This discussion will include a strategy that I developed for SDRAF placement, as well as an experimental demonstration. So far, DSA has not been deployed commercially for semiconductor manufacturing, and much of the existing work on DSA does not account for the specific challenges of patterning practical devices with DSA. In discussing my work on patterning a PCM array using DSA and on an SDRAF insertion strategy, I highlight some DSA integration challenges and delve into possible routes to solve them. Through this work, I show that DSA can be used to pattern memory and logic and point researchers toward important considerations for future demonstrations of DSA-patterned devices.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2022; ©2022 |
| Publication date | 2022; 2022 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Tung, Maryann Chenting |
|---|---|
| Degree supervisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Howe, Roger Thomas |
| Thesis advisor | Pop, Eric |
| Degree committee member | Howe, Roger Thomas |
| Degree committee member | Pop, Eric |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Maryann Chenting Tung. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2022. |
| Location | https://purl.stanford.edu/yd977gg1401 |
Access conditions
- Copyright
- © 2022 by Maryann Chenting Tung
- License
- This work is licensed under a Creative Commons Attribution 3.0 Unported license (CC BY).
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