Model validation of mixed-signal systems
Abstract/Contents
- Abstract
- Today it is difficult to validate a mixed-signal System-on-Chip, i.e., one which contains analog and digital components. The problem is that the analog and digital subsystems are usually strongly intertwined so they must be validated together as a system, but the validation approach for analog and digital blocks are completely different. We address this problem by creating high-level functional models of the analog components that are compatible with top-level digital system validation, and then providing a method of formal checking to ensure that these functional models match the operation of the transistor level implementations of these blocks. The formal checking of the functional analog models is enabled by observing that the result surface of an analog block is a smooth function of its analog inputs -- that is what makes it an analog block. This smooth result surface means it is not difficult to "explore" the design space of an analog block. We use this insight to create an equivalence checker between two analog descriptions: a SPICE netlist and its Verilog model. This checker exploits the fact that most analog circuits have a linear intent. Lastly we use this same insight to simplify statistical analysis of large mixed-signal systems to ensure that the system is robust to process variations. We describe a way to characterize the statistical behavior of circuits and to map the results to the functional model so one can estimate the parametric yield of the system by running system-level Monte Carlo simulations with analog models instead of circuit netlists.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Lim, Byong Chan |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Horowitz, Mark (Mark Alan) |
| Primary advisor | Murmann, Boris |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Advisor | Wooley, Bruce A, 1943- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Byong Chan Lim. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Byong Chan Lim
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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