Surface passivation and junction engineering in silicon / germanium metal-oxide-semiconductor field-effect-transistors for high performance application
Abstract/Contents
- Abstract
- The planar silicon MOSFET is facing diminishing performance returns in improvement from device geometry scaling. Two alternative devices are being explored as possible solutions to this problem. The first contender is a multi-gate device (FINFET or surround gate) and the other is a MOSFET with high mobility channel material such as germanium, III-V or carbon. Ge has emerged as an important materials platform during recent years. With its high carrier mobility and the ability to detect and emit photons at telecommunications wavelengths, Ge is an attractive candidate for applications in both high performance electronics and optoelectronics. Moreover due to its compatibility with conventional CMOS fabrication, it can be processed using the standard manufacturing techniques that are currently used for silicon. However Ge does present a number of unique challenges that must be overcome, including issues of surface passivation, low n-type dopant solubility, and high dopant diffusivity. In this work, the unique properties of surface passivation enabled by radical oxidation are discussed. Some of the highlights are low temperature processing, substrate orientation independent growth rate of dielectric and low interface density. Subsequently, this radical oxidation is applied to 3D vertical gate all around (GAA) silicon MOSFET devices. Higher drive current, lower gate leakage and higher gate dielectric breakdown voltage are demonstrated for GAA devices using radical oxidation in comparison to thermal oxidation In the second part, radical oxidation is investigated for GeO2 growth as an interfacial layer in high-k / Ge gate stack. Using MOSCAP and n-MOSFET devices on Ge, low interface state density combined with drive current and electron mobility enhancement is demonstrated for Ge devices. In the third part, the source/drain junctions for Ge are studied. Ultra-shallow junctions using plasma immersion ion implantation are demonstrated. High n-type dopant activation in Ge using laser annealing is realized along with high performance diodes, significant reduction of contact resistance and integration in a MOSFET process flow.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Thareja, Gaurav |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | McIntyre, Paul Cameron |
| Thesis advisor | Saraswat, Krishna |
| Advisor | McIntyre, Paul Cameron |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Gaurav Thareja. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Gaurav Thareja
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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