III-V material integration in 1-transistor capacitor-less DRAM
Abstract/Contents
- Abstract
- Scaling of the capacitor in present 1-transistor 1-capacitor dynamic random access memory (1T-1C DRAM) technology has become increasingly challenging. The fabrication of this capacitor itself costs about 25% of the total cell cost and also decreases yield and reliability. Recently the embedded DRAM technology has become mainstream. In this technology, the logic transistor and the DRAM cell fabrication processes are integrated together. From this point of view, the 1-transistor capacitor-less DRAM (1T-DRAM) technology is quite attractive. It attempts to stores charge inside the transistor body instead of a capacitor to distinguish between logic state '0' and '1'. Thus this technology eliminates the need for a capacitor. However the retention time has always been an issue with silicon based capacitor-less DRAM technology and hence this technology has not been adopted in current CMOS industry. In this work we identify the inadequate charge storage capability as the main culprit for short retention time in silicon-based 1T-DRAM. We propose to use gallium phosphide (GaP) at source and drain (GaP-SD). GaP has a large valence band-offset (0.8-1 eV) and close lattice constant (0.37% mismatch) to silicon. This band-offset increases the hole storage capability and retention time of the transistor but does not affect its speed of operation to a great extent. Using TCAD simulations, we evaluate different GaP-SD 1T-DRAM structures suitable for commodity and embedded DRAM (for bulk and SOI) technology and show their superiority to pure silicon based 1T-DRAM in terms of scalability and the retention time performance. Our simulations show that the performance can be further enhanced by inserting a germanium layer in the silicon channel. To fabricate GaP source-drain transistors, we first optimize the growth of a thin and strained GaP film on bulk Si substrate using metal-organic chemical vapor deposition (MOCVD) technique. We evaluate the GaP film and Si-GaP p-n heterojunction interface using different physical characterization techniques (SEM, XRD, AFM, TEM) and also by electrically characterizing the GaP-Si heterojunction diode. Next, long channel transistors on bulk silicon substrate with GaP source-drain and silicon channel are fabricated to show the proper functioning of GaP as source and drain material. Finally, using optical excitation as a method of hole generation, we confirm the enhanced hole storage capability of the GaP-SD transistor, thus validating the efficiency of the GaP-Si valence band offset.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2015 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Pal, Ashish |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Saraswat, Krishna |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Nainani, Aneesh |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Plummer, James D |
| Advisor | Nainani, Aneesh |
| Advisor | Nishi, Yoshio, 1940- |
| Advisor | Plummer, James D |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Ashish Pal. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2015. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2015 by Ashish Pal
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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