CMOS technology assessment and optimization : from device and interconnect modeling to system performance evaluation
Abstract/Contents
- Abstract
- Complementary Metal-Oxide Semiconductor (CMOS) technology scaling has been the main driving force behind the rapid growth of the electronics industry for more than five decades, ever since Moore's Law was proposed in 1965. In the early days, downsizing transistors not only increased the transistor density on a chip, but also enhanced the logic speed while the power density remained the same following the so-called Dennard scaling. In the recent decade, however, the performance gain with scaling has been gradually diminished due to non-ideal effects such as the short-channel effect, non-scalable gate oxide thickness and supply voltage, and non-negligible parasitic and interconnect resistance and capacitance. While many new transistor and interconnect technologies have been proposed to maintain the historical rate of performance and density improvement, their impact on the system-level performance in the sub-10-nm regime is unclear. Technology assessment at early development stage is a non-trivial task as new technologies are often not mature enough to provide sufficient data, yet the high cost of developing a new technology makes it vital to gain an early understanding of their potential benefits. Early insights into the key performance detractors will help focus technology development efforts so resources can be directed toward the most important challenges. Therefore, this thesis aims to develop compact models for emerging transistors and a suite of tools for implementation of very-large-scale integration (VLSI) systems to enable early assessment of new technology options from a holistic device-to-system perspective. In the first part of this thesis, a compact virtual-source (VS) model for Carbon Nanotube (CNT) Field-Effect Transistors (CNFETs) is presented. To assess the device-level performance in the sub-10-nm technology nodes, the VS model is fitted to experimental data of CNFETs with gate lengths down to 15 nm to extract carrier mobility and velocity. Then to account for dimensional scaling, the short-channel effect, direct source-to-drain tunneling leakage current, parasitic metal-to-CNT contact resistances, and CNT quantum capacitance are considered in the model. Dependencies of the device current and capacitance on the physical dimensions such as the gate length, gate oxide thickness, and CNT diameter are also captured. To compensate for the lack of experimental data, physics-based numerical simulations are used to calibrate the model. The model is then used to optimize CNFETs and evaluate the transistor gate delay at a contacted gate pitch of 31 nm corresponding to the target in 2023 projected by the 2013 ITRS. The requirement for CNT density to meet the delay target is studied as a guide for CNFET development. A VLSI circuit is formed by interconnecting millions of transistors by metal wires and vias. To keep increasing the transistor density, the dimensions of interconnect wires and vias must be scaled as well, resulting in a rapid increase in interconnect resistances. As the impact of interconnects on system performance becomes increasingly significant, component-level assessment of a CMOS technology becomes insufficient. Small benchmark circuits such as ring oscillators or adders often fail to capture the complexity of interconnects. A holistic approach that includes both transistors and interconnects in the context of VLSI systems is thus required for accurate technology assessment. We develop a Device-to-System Performance EvaLuation (DISPEL) tool that integrates device/interconnect modeling and physical design flow to address this issue. The detailed placement and routing optimization enable realistic analysis of the complex interconnects and their impact on the system-level power, speed, and area. The DISPEL tool is then used to implement a 32-bit commercial processor core at a projected 5-nm node to assess different transistor and interconnect technology options, including Si nanowire, MoS2, black phosphorous FETs and graphene as interconnect wires. Using the data generated by DISPEL, feedforward neural networks are trained to predict the core performance without going through the time-consuming physical design flow. In contributing the above, this thesis aims to bridge the gap between technology developers and circuit/system designers to facilitate the development of new transistor and interconnect technologies, through technology-level modeling and system-driven evaluation approaches.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2017 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Lee, Chi-Shuen |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Advisor | Pop, Eric |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Chi-Shuen Lee. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2017. |
| Location | https://purl.stanford.edu/wt566wz1515 |
Access conditions
- Copyright
- © 2017 by Chi-Shuen Lee
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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