Efficient microarchitecture for network-on-chip routers
Abstract/Contents
- Abstract
- Continuing advances in semiconductor technology, coupled with an increasing concern for energy efficiency, have led to an industry-wide shift in focus towards modular designs that leverage parallelism in order to meet performance goals. Networks-on-Chip (NoCs) are widely regarded as a promising approach for addressing the communication challenges associated with future Chip Multi-Processors (CMPs) in the face of further increases in integration density. In the present thesis, we investigate implementation aspects and design trade-offs in the context of routers for NoC applications. In particular, our focus is on developing efficient control logic for high-performance router implementations. Using parameterized RTL implementations, we first evaluate representative Virtual Channel (VC) and switch allocator architectures in terms of matching quality, delay, area and power. We also investigate the sensitivity of these properties to key network parameters, as well as the impact of allocation on overall network performance. Based on the results of this study, we propose microarchitectural modifications that improve delay, area and energy efficiency: Sparse VC allocation reduces the complexity of VC allocators by exploiting restrictions on transitions between packet classes. Two improved schemes for speculative switch allocation improve delay and cost while maintaining the critical latency improvements at low to medium load; this is achieved by incurring a minimal loss in throughput near the saturation point. We also investigate a practical implementation of combined VC and switch allocation and its impact on network cost and performance. The second part of the thesis focuses on router input buffer management. We explore the design trade-offs involved in choosing a buffer organization, and we evaluate practical static and dynamic buffer management schemes and their impact on network performance and cost. We furthermore show that buffer sharing can lead to severe performance degradation in the presence of congestion. To address this problem, we introduce Adaptive Backpressure (ABP), a novel scheme that improves the utilization of dynamically managed router input buffers by varying the stiffness of the flow control feedback loop based on downstream congestion. By inhibiting unproductive buffer occupancy, this mitigates undesired interference effects between workloads with differing performance characteristics.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Becker, Daniel Ulf |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Dally, William |
| Thesis advisor | Dally, William |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Thesis advisor | Olukotun, Oyekunle Ayinde |
| Advisor | Kozyrakis, Christoforos, 1974- |
| Advisor | Olukotun, Oyekunle Ayinde |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Daniel U. Becker. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Daniel Ulf Becker
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