Post-silicon bug localization in processors
Abstract/Contents
- Abstract
- For complex integrated circuits, pre-silicon verification alone is inadequate in ensuring that manufactured chips do not contain logic and electrical bugs. Post-silicon validation, which operates samples of manufactured chips in application environments to validate correct behaviors across specified operating conditions, is essential. According to industry reports, post-silicon validation is becoming very expensive. A major bottleneck in post-silicon validation is the bug localization step which involves identifying hardware bug locations and short functional stimuli that can expose detected bugs. For example, it may take several days to weeks to localize an electrical bug that may arise due to incorrect interactions between a design and the operating conditions. This dissertation presents IFRA (Instruction Footprint Recording & Analysis), a new technique for post-silicon bug localization in processors, which overcomes cost and scalability challenges of existing techniques. During normal operation of a processor in a post-silicon validation setup, special on-chip recorders collect information about flows of instructions through the processor and what the instructions did as they passed through various design blocks. Upon system failure, such as a crash, the recorded information is scanned out and analyzed offline using special self-consistency-based analysis techniques to localize hardware bugs. IFRA provides two major benefits over traditional techniques: (1) it does not require bugs to be reproduced at the system-level and (2) it does not require system-level simulation. Evaluation of IFRA on an open-source microarchitectural simulator modeling Alpha 21264 demonstrates high bug localization accuracy (96%) at low area overhead (1%). Applying IFRA to new microarchitectures can be challenging because it requires some degree of manual effort. This dissertation will also present a new BLoG (Bug Localization Graph) technique which is a step towards automated application of IFRA. Evaluation of BLoG-assisted IFRA on an industrial microarchitectural simulator modeling Intel Core i7, a state-of-the-art complex commercial processor, demonstrates its effectiveness (90% bug localization accuracy) and practicality.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Park, Sung-Boem |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Dill, David L |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Advisor | Dill, David L |
| Advisor | Kozyrakis, Christoforos, 1974- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Sung-Boem Park. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Sung Boem Park
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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