CMOS-compatible strain engineering and device scaling of monolayer molybdenum disulfide transistors
Abstract/Contents
- Abstract
- Moore's Law has been the driving factor behind the exponential growth of the semiconductor industry over the past six decades. As the reduction of silicon features approaches the atomic limit, we are once again at an inflection point, requiring researchers to investigate new ultrathin semiconductors to overcome these limitations. Monolayer transition metal dichalcogenides (TMDs) are a class of atomically-thin materials which have demonstrated promise for nano-scaled transistors owing to their excellent electrical properties in this regime. In silicon technology, the first great advance beyond conventional scaling came from harnessing strain to improve performance. Strain is also known to affect the band gap of TMDs but has rarely been investigated in TMD transistors on rigid substrates. In the first part of this thesis, I explore how electron beam evaporation, the most commonly used technique for contact formation to TMDs, can introduce significant tensile strain to monolayer molybdenum disulfide (MoS2). Next, I demonstrate a fully industry-compatible approach to impart strain to two-dimensional TMD transistors using tensile-stressed silicon nitride capping layers. I apply it to both back and dual-gated devices, demonstrating improvements up to 60% in the on-state current of monolayer MoS2 transistors. The next major advance in silicon technology came from the introduction of high-κ /metal gate technology, offering improved gate control. In the final part of this thesis, I developed a process which allows the integration of monolayer MoS2 on thin, high-κ dielectrics which enables lower voltage operation, improved subthreshold behavior and drive currents up to ~700 μA/μm at a channel length of 50 nm. Together, these results offer a holistic approach to channel and contact engineering, offering a path for TMD transistors to become industrially relevant.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2023; ©2023 |
| Publication date | 2023; 2023 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Jaikissoon, Marc David Kavir |
|---|---|
| Degree supervisor | Saraswat, Krishna |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Pop, Eric |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, School of Engineering |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Marc David Jaikissoon. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2023. |
| Location | https://purl.stanford.edu/vn283dz5986 |
Access conditions
- Copyright
- © 2023 by Marc David Kavir Jaikissoon
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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