Exploring abstract interfaces in system-on-chip integration
Abstract/Contents
- Abstract
- Modern mobile devices are marvels of computation. They can encode high-definition video, processing and compressing over 350MB/s of image data in real time. They have no trouble driving displays with as much resolution as a full laptop, and smart-phone manufacturers boast of running games with ``console quality'' graphics. Mobile devices pack all of this computational power into a 1-2W hand-held package by integrating a number of specialized hardware accelerators (IP) along with conventional CPU and GPUs in a system-on-chip (SoC). Unfortunately, creating these specialized systems is becoming increasingly expensive. Since hardware accelerators come from a number of different sources and design cycles, different accelerator blocks will often contain incompatible hardware interfaces. Therefore, a large portion of SoC design cost comes in the form of designers manually interfacing each accelerator into a system. This work includes everything from building custom logic to wire up a block, to developing the drivers and API needed to take advantage of the hardware. My research focuses on generating these interfaces, including the physical hardware used to tie IP blocks into a system and the associated software collateral. Leveraging recent trends such as High Level Synthesis and other hardware ``generator'' methodologies, I propose an IP interface abstraction and parameterization designed to describe the interface of most current IP blocks. By encoding this knowledge at a higher-level of abstraction, I am able to construct and demonstrate a hardware generator that maps an interface protocol description into synthesizable register transfer language (RTL), and that can automatically create hardware bridges between different interconnect standards. To ease the integration of the next generation of IP blocks---blocks that are automatically generated based off of user specification---I propose a set of interface primitives. When integrated into an IP generator, these primitives can automatically generate an interface that my interface system can tie to the rest of the system. I also demonstrate how the information stored in these types of primitives can be used to automatically generate a low-level software driver that manages access to the IP blocks. Finally, I show how the simulation environment provided with an IP generator can be used to provide a domain appropriate application programming interface (API) to drive the software. Using an image signal processor generator as my platform, I demonstrate the construction of a map between the simulation software and hardware driver that enables a full one-button flow from algorithm development to applications running on specialized hardware within a working system.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Danowitz, Andrew |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Thesis advisor | Richardson, Stephen |
| Advisor | Kozyrakis, Christoforos, 1974- |
| Advisor | Richardson, Stephen |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Andrew Danowitz. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Andrew Robert Danowitz
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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