Active messages for speed, scalability, and efficiency
Abstract/Contents
- Abstract
- Integrating active messages onto many-core chip multiprocessors (CMPs) increases the speed, efficiency, and scalability of parallel programs. In traditional shared-memory CMPs, communication is handled implicitly and inefficiently by the hardware cache coherency protocol. Active messages, those that trigger remote atomic execution of custom handlers, give the programmer explicit control of communication and computation location. This dissertation describes the implementation, enumerates five usage idioms, and quantifies the benefits of on-chip active messages. Full programs run 63% faster, have 2.2x less network traffic, and consume 11% less energy on a 256 core CMP when using active messages.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Harting, Richard Curtis |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Dally, William |
| Thesis advisor | Dally, William |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Thesis advisor | Kozyrakis, Christoforos, 1974- |
| Advisor | Horowitz, Mark (Mark Alan) |
| Advisor | Kozyrakis, Christoforos, 1974- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | R. Curtis Harting. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Richard Curtis Harting
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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