2D materials for logic and memory integration
Abstract/Contents
- Abstract
- Today's data-driven applications, such as big data analytics, neural networks, and machine learning, require huge memory and computing resources. The latency and energy incurred for data movement between processing unit and memory has become a significant limitation (known as the "memory wall") as traditional techniques such as caching are no longer effective for the data-intensive applications that dominate modern computing. Solving the "memory wall" problem requires future computer technology to directly integrate memory and transistor devices with high density vertical interconnect accesses (vias) to provide parallel, high bandwidth memory access. However, the high temperature of silicon processing is not compatible with this 3D monolithic integration. A desired low temperature integration can be achieved by using two-dimensional (2D) materials which have intrinsically layered and flat atomic structures, because devices made of 2D materials can be fabricated at lower temperatures. This thesis introduces three exploratory studies on advancing 2D materials for developing 3D monolithic integrated systems. First, I focused on improving transistor performance and studied high-mobility 2D material black phosphorous (BP) transistors using various metals as the contact metal. This work achieved unipolar n-type BP transistors by using ultra-low work function metals, demonstrating record high n-type current. Furthermore, the study revealed the physical mechanisms of controlling doping and de-pinning effects for n- and p- type BP transistors. Beyond transistor studies, I then demonstrated the first 3D sequential monolithic integrated two levels of 1-transistor-1-resistor (1T1R) memory cells. The cell is fabricated entirely using 2D materials: hexagonal-Boron Nitride (hBN) serves as the resistive switching memory cell and monolayer Molybdenum Disulfide (MoS2) serves as the channel material for the transistor selector. In order to achieve a high-density memory array, a two-terminal selector with a high nonlinear current-voltage characteristic is necessary. I developed a new two-terminal selector utilizing a 2D material heterostructure with an H-shape energy barrier. This new device design in theory should have high on-state current density and virtually unlimited endurance due to its quantum tunneling mechanism. Our results characterized the first out-of-plane current through an ultra-thin (3 monolayer) heterojunction and provide the critical foundation for a high endurance selector using a 2D heterojunction. Due to the transferable feature of 2D materials, these processes can be easily adopted for 3D monolithic integrated transistors and memories in multiple logic and memory layers connected vertically by fine-grained nanoscale vias, thereby overcoming the "memory wall.".
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2020; ©2020 |
| Publication date | 2020; 2020 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Wang, Ching-Hua |
|---|---|
| Degree supervisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Degree committee member | Pop, Eric |
| Degree committee member | Saraswat, Krishna |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Ching-Hua Wang |
|---|---|
| Note | Submitted to the Department of Electrical Engineering |
| Thesis | Thesis Ph.D. Stanford University 2020 |
| Location | https://purl.stanford.edu/sx873sn0026 |
Access conditions
- Copyright
- © 2020 by Ching-Hua Wang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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