RRAM SPICE Model with Three Model Levels

Developing resistive random access memory (RRAM) SPICE models that capture and generalize the essential device characteristics is important for circuit and system design. Moreover, having multiple model levels with a hierarchy of complexity and physics realism can be greatly beneficial to meet diverse design objectives and constraints. Here, we develop a three-level SPICE model coded in Verilog-A. HSPICE is used to compile Verilog-A and produce various simulation results calibrated with experimental measurements.

[1] H. Li, T. Wu, S. Mitra, and H.-S. P. Wong, “Resistive RAM-centric computing: Design and modeling methodology,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2263-2273, Sep. 2017.
[2] H. Li, Z. Jiang, P. Huang, Y. Wu, H.-Y. Chen, B. Gao, X. Liu, J. Kang, and H.-S. P. Wong, “Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model,” Design, Automation & Test in Europe (DATE), pp. 1425-1430, 2015.