Realizing ultralow-leakage monolayer and highly P-type bilayer transition metal dichalcogenide transistors
Abstract/Contents
- Abstract
- For decades, Moore's Law has driven great improvements in the density, performance, and price of silicon electronics. This pace, however, has slowed as silicon reaches atomic limits, e.g. mobility degradation as a result of surface roughness scattering. Two-dimensional (2D) semiconductors, in particular atomically-thin transition metal dichalcogenides (TMDs), could overcome some of the limitations of silicon electronics. While n-type TMD transistors with relatively good on-state have been demonstrated, their off-state and p-type regimes have been broadly underexplored. In this work, I have investigated these regions of 2D TMD transistor behavior. First, I provide an overview on the growth of monolayer TMDs by chemical vapor deposition and the methods with which we can non-destructively characterize them. This allows for the direct synthesis of large-area, 2D materials for electronic study. I highlight that this process can even deposit monolayers onto non-planar substrates, such as three dimensional sidewalls or deep trenches. Next, I discuss our study of the extremely low currents achievable in the off-state of monolayer TMD transistors, enabled by their band gap which is approximately twice that of silicon. These were measured by fabricating ultrawide (~ 1 mm) devices, enabling the detection of currents as low as 10 aA/μm, four orders of magnitude lower than possible in silicon, at room temperature. We also use temperature-dependent measurements and modeling to explore the fundamental limits of leakage currents in these 2D semiconductors. Finally, I focus on recent work developing p-type TMD transistors, which are necessary to achieve 2D CMOS technology, by utilizing bilayer WSe2. These bilayer devices show significant increases in hole mobility and current drive compared to monolayers. I discuss the possible mechanisms for this improvement, such as change in band structure and material resilience to fabrication. This work suggests that monolayers may not always be the most optimal channel thickness for TMD transistors, particularly p-type. Taken together, our results reveal an interesting trade-off between high-performance and low-power devices with layer number in 2D electronics.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2023; ©2023 |
| Publication date | 2023; 2023 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Bailey, Connor Scott |
|---|---|
| Degree supervisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Saraswat, Krishna |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, School of Engineering |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Connor Scott Bailey. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2023. |
| Location | https://purl.stanford.edu/sc567ds0471 |
Access conditions
- Copyright
- © 2023 by Connor Scott Bailey
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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