High-speed D/A conversion in FinFET CMOS technology
Abstract/Contents
- Abstract
- Digital-to-analog converters (DACs) are crucial building blocks in modern communication systems like wireline transceivers and digital mm-wave phased arrays. These applications drive steady increases in bandwidth, channel count, as well as integration density, which mandates data converters that are compatible with the latest CMOS technology. For analog-to-digital converters (ADCs), this has led to an architectural shift toward time-interleaved successive approximation, which exploits the strengths of modern CMOS while mitigating its weaknesses. On the other hand, DACs have not significantly changed since the 1970s and predominantly rely on the current steering (CS) topology. We discuss an alternative approach for high-speed (> 10 GS/s), moderate-resolution (6-8 bit) DACs, with the specific goals of reducing chip area and improving FinFET CMOS compatibility. Our DAC uses a switched capacitor (SC) architecture that separates the functions of level generation, timing/combining, and output power delivery, which are lumped into a single node in a conventional CS DAC. In the proposed DAC, levels are generated using time-interleaved SC DAC cores with sub-femtofarad unit capacitors, which offer sufficient linearity and noise performance at the 8-bit target resolution. The cores' outputs are combined and re-timed downstream and the final 50 Ohm load is driven by an inverter-based buffer. To validate this new approach, we implemented a series of 8-bit prototype DACs in 16 nm FinFET CMOS, operating at 14 GS/s, 28 GS/s (2x time-interleaved) and 56 GS/s (4x delta-interleaved), respectively. These designs show competitive performance while achieving up to 10x area advantage over the state of the art.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2022; ©2022 |
| Publication date | 2022; 2022 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Caragiulo, Pietro |
|---|---|
| Degree supervisor | Murmann, Boris |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Degree committee member | Arbabian, Amin |
| Degree committee member | Horowitz, Mark (Mark Alan) |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Pietro Caragiulo. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2022. |
| Location | https://purl.stanford.edu/rz812rb9519 |
Access conditions
- Copyright
- © 2022 by Pietro Caragiulo
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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