Atomic-layer-deposited high-k gate oxides on germanium : interface engineering for scaled metal-oxide-semiconductor devices
Abstract/Contents
- Abstract
- Germanium (Ge) has emerged as a promising candidate for surface channels in highly-scaled field-effect-transistors (FETs), as performance and reliability issues are likely to limit the use of conventional Si-based complementary-metal-oxide-semiconductor (CMOS) transistors beyond the 15nm technology node. Lack of a high quality and stable thermal oxide of germanium has prompted interest in the use of high-k (high dielectric-constant) gate dielectrics on Ge channels. An interface passivation layer (IPL) between the high-k film and the Ge substrate appears to be necessary to avoid large defect densities characteristic of atomically-abrupt high-k (ZrO2 or HfO2)/Ge interfaces. Atomic layer deposition (ALD) is a useful high-k metal oxide film growth technique due to the precise nature of thickness control and uniformity of thickness for ultra-thin films. The use of ALD to synthesize deposited IPLs interposed between the Ge channel and an overlying high-k layer has not been studied extensively. For this research, a laboratory-scale ALD reactor was designed and built for Al2O3 and TiO2 chemistries with liquid metal organic precursors and H2O as oxidant. A novel in situ x-ray photoelectron spectroscopy (XPS) setup that uses a differentially pumped electrons lens and analyzer was incorporated successfully into the ALD growth chamber, enabling the real-time monitoring of chemical states in the ALD ambient. This system demonstrated collection of in situ spectra within 10's of seconds of an ALD precursor pulse, without moving the substrate or changing its temperature. Pre-ALD Ge surface functionalization by in situ oxidant dosing ("pre-pulsing") in the growth chamber was studied and optimized to synthesize a high-quality ALD-Al2O3/Ge interface, with a midgap density of interface states (Dit) ~ 2x1011 cm-2 eV-1. In situ XPS studies revealed the influence of hydroxyl (-OH) termination of the Ge surface in passivating dangling bonds that lead to fast trapping. The evolution of Ge-O bonding states during pre-pulsing was correlated with the observed improvements in hysteresis, frequency dispersion of the gate capacitance, and the response of fast (band-edge) and slow (midgap) interface states. The effects of scaling the physical thickness of the ALD-Al2O3 down to the sub-nanometer regime on key electrical parameters such as Dit, capacitance density, leakage current density and fixed charge were studied. The ultra-thin ALD-Al2O3/Ge interface, unlike in Si, was observed to resist sub-cutaneous oxidation, evidencing the capacitance scaling potential of these IPLs. Photoemission studies done using synchrotron radiation suggested a possible mechanism for FGA-induced passivation of interface states and revealed excellent valence and conduction band offsets of ALD-Al2O3 to Ge (> 2.5eV). Thus, unlike oxide or oxynitride passivation, ALD-Al2O3 IPLs promise an effective leakage barrier to hole and electron injection in addition to providing low Dit. Aggressive gate capacitance scaling requirements for future CMOS technology necessitates the use of the so-called "higher-k" dielectrics such as TiO2 (k > 25) in the gate stack. However, the conduction band offset of the TiO2/Ge interface is very low (~ 0.2eV), resulting in unacceptably high gate leakage. To this end, successful integration of ultrathin (~ 1 nm), interface-engineered ALD-Al2O3 IPLs in ALD-TiO2 gate dielectric stacks on Ge was demonstrated through detailed physical and electrical characterization studies. These IPLs, owing to their large bandgap (~ 6.6eV), were observed to dramatically reduce the gate leakage at the TiO2/Ge interface by 6 orders of magnitude at the flatband voltage. The Platinum-gated bilayer devices exhibited excellent C-V characteristics down to a CET of 1.2nm and exhibited a minimum Dit ~ 3x1011 cm-2 eV-1 near midgap after FGA. Taking into account a typical 0.4nm contribution due to the quantum capacitance of the Ge substrate, these devices are well-suited to achieve the sub-nanometer scaling benchmarks for the 22nm node and beyond. Extensive temperature- and frequency-dependent defect characterization of the bilayer devices evidenced an unpinned oxide/semiconductor interface and showed that thermally-activated electron transport into shallow defect states in the TiO2 (~0.25eV below the CB edge) near the TiO2/Al2O3 interface resulted in a temperature-dependent dispersion of the accumulation capacitance density.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Swaminathan, Shankar |
|---|---|
| Associated with | Stanford University, Department of Materials Science and Engineering |
| Primary advisor | McIntyre, Paul Cameron |
| Thesis advisor | McIntyre, Paul Cameron |
| Thesis advisor | Pianetta, Piero |
| Thesis advisor | Saraswat, Krishna |
| Advisor | Pianetta, Piero |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Shankar Swaminathan. |
|---|---|
| Note | Submitted to the Department of Materials Science and Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Shankar Swaminathan
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