A solid-state doping technology for carbon nanotubes
Abstract/Contents
- Abstract
- Single wall carbon nanotubes (SWCNTs) have great potential of becoming the channel material for future high-speed transistor technology. Despite tremendous progress in the recent years, certain challenges still remain to be addressed to realize a scaled CNT based transistor technology. In this thesis I address three fundamental challenges that are essential to realizing a SWCNT-based transistor technology. One of the fundamental issues in carbon nanotube transistor technology originates from material synthesis which provides us a mixture of metallic and semiconducting CNTs. To use the semiconducting CNT as the transistor channel material, we developed a solution-based carbon nanotube sorting process where semiconducting CNTs can be sorted from metallic CNTs to a > 99% of purity. The main application of CNTs following this sorting process is for thin film transistors (TFTs) that can be utilized on flexible transparent substrates. In order to achieve carbon nanotube field effect transistors (CNTFETs) with excellent gate control, it is essential to understand the interactions between CNTs and gate insulation materials - ALD high-k dielectrics. In the second section I will investigate the effects of atomic layer deposited (ALD) high-k dielectrics (Al2O3 & HfO2) on SWCNTs. We study the ALD nucleation and growth on SWCNTs and we confirm our findings and gain insightful information using Raman Spectroscopy. In the third part of the thesis I present a novel, VLSI-compatible solid-state doping technique to fabricate n-type carbon nanotube transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit excellent n-type behavior. We confirm this mechanism by carrying out a variety of characterization techniques and provide a general guideline for CNT doping that could also be applicable for MoS2 and graphene. This thesis paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Suriyasena Liyanage, Luckshitha |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Bao, Zhenan |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Advisor | Bao, Zhenan |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Luckshitha Suriyasena Liyanage. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Luckshitha Suriyasena Liyanage
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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