Two-dimensional devices and interfaces : from fundamentals to system models
Abstract/Contents
- Abstract
- Atomically-thin two-dimensional (2D) semiconductors like MoS2, with a variety of unique electronic properties, have attracted significant attention for applications in nanoelectronics, memory, and logic. This thesis explores, from a theoretical as well as a technological point of view, the challenges faced by 2D transistor technology. First, we will discuss the electrostatics of a field-effect transistor (FET) in the limit of atomically thin (sub-nanometer) channels. We show that the scale length in double-gate FETs based on 2D semiconductors primarily depends on the physical thickness of the gate oxide and not on the oxide dielectric constant. In addition to the scale length, we also reveal the impact of the fringing field, contact architecture, and the device geometry on short channel effects in the transistor. Using our theory, we explain the drain-induced barrier lowering observed in fabricated 2D FETs with a channel length of 20 nm. Next, we systematically study electrical contacts to 2D materials, which are presently limiting the performance of 2D FETs. We show that the Landauer-Büttiker (ballistic) limit for the contact resistance to monolayer MoS2 is ~10 Ω∙μm at a carrier density of 1e13 cm-2. However, the best experimental contact resistance measured to date for gold to MoS2 at similar carrier density is ~300 times higher. To understand this discrepancy, we explore the role of current crowding as well as the intrinsic contact resistivity. Simulations indicate that current crowding can be reduced by ~77% if the semiconductor below the contact is patterned to optimize edge injection. However, experimental gold contacts to MoS2 are likely limited by poor interfacial carrier transmission. This carrier transmission can be improved by reducing the van der Waals (vdW) gap between gold and MoS2, and reducing the Schottky barrier height. Ab initio simulations reveal the role of interfacial chemistry on vdW gap and Schottky barrier height, and provide guidelines to engineer the contact resistance. Later, we study the thermal transport across 2D-insulator and 2D-2D interfaces. Based on detailed molecular dynamics simulations, we show that the thermal boundary conductance (TBC) for monolayer MoS2 on SiO2 and MoS2 on AlN are of the order of ~10 MWm-2K-1, which is near the lower limits of TBCs known for solid-solid interfaces. We study the dependence of TBC based on vdW interaction strength, number of 2D layers, and v temperature. The TBC can be manipulated by varying the vdW interaction strength as well as matching the phonon modes between the 2D material and the substrate. Based on these intuitions, we develop a simple Landauer transport model to explain the experimental trend in TBCs for various 2D-2D and 2D-3D interfaces. Finally, we develop physics-based and experimentally-calibrated compact models for long channel (diffusive) and short channel (quasi-ballistic) 2D FETs. We show that device self-heating and temperature effects are crucial to model the carrier transport accurately. Using our models and experimentally measured data for device-to-device variations, we perform Monte Carlo simulations and reveal that simple circuits and systems made from n-type 2D FETs are expected to have surprisingly low variation even at scaled technology nodes. Both of our models are developed in Verilog-A and are publicly available online. Such models are necessary to enable the design, optimization, and fabrication of large circuits, which are the next steps in the development of 2D electronics. In summary, this thesis uses a simulation-driven approach along with experiments to address critical bottlenecks for 2D transistor technology.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2018; ©2018 |
| Publication date | 2018; 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Suryavanshi, Saurabh Vinayak |
|---|---|
| Degree supervisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Saraswat, Krishna |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Saurabh Vinayak Suryavanshi. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2018. |
| Location | https://purl.stanford.edu/ps346kg3738 |
Access conditions
- Copyright
- © 2018 by Saurabh Vinayak Suryavanshi
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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