Copper sulfide resistance change memory and its scalability
Abstract/Contents
- Abstract
- The increase of portable electronic devices such as cellular phones, digital cameras, and mp3 players is driving a rapid growth of the market for nonvolatile memories (NVMs). Today's most established NVM technologies are based on charge storage method. However, the scaling of current NVM technologies beyond 32 nm node of International Technology Roadmap for Semiconductors (ITRS) poses severe problems such as poor retention and unacceptable cross-talks among devices. To overcome these disadvantages and achieve high-speed, high-density, long-retention, and low-power NVMs, several new memory materials and technologies have been extensively investigated. Among new emerging materials and concepts, we investigate copper sulfide resistance change memory, which is one of the most promising candidates for future NMV, whose electrical resistance can be changed reversibly between two stable states. In the first part of the study, we report fabrication and electrical characterization of micrometer-scale copper sulfide NVM devices. We have achieved synthesis of stoichiometric Cu2S using anodic polarization whose composition is analyzed by Rutherford backscattering (RBS), and fabricated [micrometer]-sized NVM devices in the sandwiched structure of a Cu/Cu2S/top electrode. The resistive switching is consistent and reproducible over 50 cycles for large-area devices and 200 cycles for small-area devices. Low SET and RESET voltages below 0.3 V for switching and a high OFF-state resistance to ON-state resistance ratio over 10^5 have been achieved. The ON-state resistance value, RON, does not change as the size of the devices shrinks indicating the conduction is localized while the OFF-state resistance, ROFF, increases with the device scaling. As a result, we can obtain a fascinating scaling result that ROFF/RON ratio increases as the devices scale down. In the second part of the study, we present for the first time a simple fabrication method of copper sulfide nanopillar arrays with a high aspect ratio using nanoporous templates created from self-assembled nanostructures of block copolymers (BCP) for NVM applications. With our proposed process, the high aspect ratio of copper sulfide nanopillars with 25 nm in diameter and 170 nm in height is generated. Due to the small distance of 40 nm between the nanopillars, characterization is performed using conductive atomic force microscope (CAFM). Our nanopillar arrays exhibit a huge ROFF/RON ratio of 10^7 at a 2 [microampere] current level. This low level of switching current demonstrates the possibility of low-power NVM devices.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2013 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Kim, Sung-woo |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | McIntyre, Paul Cameron |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | McIntyre, Paul Cameron |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Sung-Woo Kim. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2013 by Sung-Woo Kim
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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