Low frequency noise in advanced CMOS technology
Abstract/Contents
- Abstract
- The main topic of this thesis is to investigate the CMOS scaling impacts on low-frequency noise properties. Such effects come from size (channel length/width) scaling, adoption of advanced doping profiles (halo pocket implantation), incorporation of alternative gate oxide (high-[Kappa]) and channel materials (SiGe). Device-level simulation capabilities have been developed to investigate low-frequency noise behavior. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation and a Hooge mobility fluctuation. Simulations based on such models have been conducted for high-[Kappa], SiGe and small gate area transistors, and the results have been correlated with experimental data, which reveals the important role of the CMOS scaling in the low-frequency noise behavior. In the study of high-[Kappa] gate dielectric it is found that carrier number fluctuation becomes the dominant noise source and the non-uniform trap energy distribution is critical to explain low frequency noise behavior. The negative impact of substrate halo doping on the low frequency noise is also studied quantitatively. Low frequency noise characteristics of Si/SiGe/Si hetero-channel MOSFETs (SiGe MOSFETs) are discussed; the study has been obtained in terms of the noise level dependence on gate bias, drain currents, and body bias, revealing the important role of the dual channels in the low-frequency noise behavior of Si/SiGe/Si hetero-channel devices. Low frequency noise characteristics in small gate area MOSFETs are studied in detail. Due to the ever decreasing gate area, the number of charge carriers in a MOSFET channel is continually going down, and single-electron low frequency noise phenomena (random telegraph noise, RTN) becomes visible, which is quite different from 1/f noise in standard MOSFETs. It is found that random telegraph noise is directly linked to Positive Bias Temperature Instability (PBTI): PBTI and RTN originate from the same physical process, charge trapping in the high-[Kappa] dielectric. The correlation between Id- and Ig-RTN is clearly observed. Ig-RTN is directly related to physical trapping or de-trapping and the Id-RTN reflects sensitivity to charge trapping as determined by gm. This dissertation has explored advanced TCAD simulations to overcome obstacles in low frequency noise and explained a comprehensive view and the underlying physics for low frequency noise in advanced CMOS technology.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Copyright date | 2011 |
| Publication date | 2010, c2011; 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Chen, Chia-Yu |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Dutton, Robert W |
| Thesis advisor | Dutton, Robert W |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Advisor | Murmann, Boris |
| Advisor | Nishi, Yoshio, 1940- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Chia-Yu Chen. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Chia-Yu Chen
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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