Variation-aware design of carbon nanotube digital VLSI circuits
Abstract/Contents
- Abstract
- Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future electronic systems. Variations specific to carbon nanotubes (CNTs) pose major obstacles to energy-efficient and robust CNFET digital VLSI. CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. CNT processing techniques alone are inadequate to overcome these challenges. We present an integrated approach, combining CNFET modeling, processing and circuit design, to create VLSI circuits tolerant to CNT variations. Probabilistic models, calibrated using experimental data, are used to analyze the effects of two major sources of CNT variations: metallic CNTs (CNTs with no / very small bandgaps) and grown CNT density variations (due to the non-uniformity in CNT positioning). Using these models, we create a probabilistic framework to derive simple yet useful CNFET processing and circuit design guidelines to overcome CNT variations. The effectiveness of this approach is demonstrated using two examples: 1. CNT variations result in functional failures of CNFET circuits. The failure probability may be reduced through CNFET sizing but at substantial energy costs. A new layout design technique, which engineers correlation among various CNFETs, reduces CNFET circuit failure probability at significantly lower costs. 2. For the first time, the impact of CNT variations on delay variations of CNFET circuits is quantified. We explore the space of CNFET sizing, together with various possibilities to improve CNFET processing, to minimize circuit delay variations at low energy costs.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2011 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Zhang, Jie |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Howe, Roger Thomas |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Howe, Roger Thomas |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Jie Zhang. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2011. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2011 by Jie Zhang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
Also listed in
Loading usage metrics...