A hardware security application of the nanoelectromechanical relay
Abstract/Contents
- Abstract
- The nanoelectromechanical (NEM) relay is a digital component that offers extremely low sub-threshold swing characteristics and has been studied by researchers in a number of universities including Stanford. Devices with low sub-threshold swing result in circuits with low power dissipation. Not only does a NEM relay gate provide substantially lower sub-threshold swing than a bulk CMOS gate, as feature sizes of these two technologies shrink going forward, the power savings of NEM relay technology vs. CMOS technology widens. Consequently, there has been active research into the feasibility of creating complete digital chips based on NEM relays. Though power savings may be a predominant application for NEM relays, this thesis explores using NEM relays for component level hardware security, a problem that has become serious as reports of chip counterfeiting have increased in recent years along with the real feasibility of successful hardware Trojan attacks. In order to thwart counterfeiters and highly intelligent, well-resourced attackers, security designs must become more sophisticated. The NEM relay is effectively an actuation device. Bias applied to the gate creates an electrostatic force that in turn causes mechanical motion that opens or closes a switch. An enhanced version of the NEM relay has a piezoelectric stack deposited on its cantilever beam with two new contacts connecting to electrodes that sandwich a thin piezoelectric film in the center of the stack. This new device, a piezoelectric NEM relay (PNR), is analyzed using a parallel-plate actuation model, a modified vibration harvester model, a distributed-parameter dynamic model, and finite element method modeling. The models show the natural response of the PNR cantilever beam to a step excitation provides an electrical signal, a damped oscillation whose frequency is structure design dependent, with sufficient duration to serve as a signature of the gate. Modules can be constructed from multiple gates that combine the signatures of each resulting in a composite module signature. Consequently, a legitimate module has a characteristic frequency domain signature that can be monitored. A hierarchal design approach can be used to create a component level device with component signatures. Signatures of a known legitimate component and a test component are compared as part of the screening process that detects corrupted parts. The end result is a digital component that provides a complex frequency domain test signal that can be used as a legitimate component signature to augment standard component test methods. Device security has been described as a continuous cat and mouse game with the forces of good working hard to stay ahead of counterfeiters and attackers. This thesis presents another tool the good forces may employ.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2015 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Watkins, John Edward |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Advisor | Howe, Roger Thomas |
| Thesis advisor | Howe, Roger Thomas |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | John Edward Watkins. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Engineering)--Stanford University, 2015. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2015 by John Edward Watkins
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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