ESD design challenges and strategies in deeply-scaled integrated circuits
Abstract/Contents
- Abstract
- It is the main objective of this work to address the scaling and design challenges of ESD protection in deeply scaled technologies. First, the thesis introduces the on-chip ESD events, the scaling and design challenges, and the nomenclatures necessary for later chapters. The ESD design window and the I/O schematics for both rail clamping and local clamping ESD schemes are illustrated. Then, the thesis delves into the investigation of the input and output driver devices and examines their robustness under ESD. The input driver's oxide breakdown levels are evaluated in deeply scaled technologies. The output driver's trigger and breakdown voltages are improved appreciably by applying circuit and device design techniques. The ESD device sections first discuss rail-based clamping, a widely used protection scheme. Two diode-based devices, namely the gated diode and substrate diode, are investigated in detail with SOI test structures. Characterization is based on DC current-voltage (I-V), Very Fast Transmission Line Pulse (VF-TLP), capacitance, and leakage measurements. Improvements in performance are realized. Technology computer aided design (TCAD) simulations help understand the physical effects and design tradeoffs. Then, the following section focuses on the local clamping scheme. Two devices, the field-effect diode (FED) and the double-well FED (DWFED), are developed and optimized in an SOI technology. Trigger circuits are designed to improve the turn-on speed. The advantages of local clamping is highlighted and compared with the rail-based clamping. The results show that the FED is a suitable option for power clamping applications and the DWFED is most suitable for pad-based local clamping. The thesis presents an ESD protection design methodology, which takes advantage of the results and techniques from pervious chapters and put each element into a useful format. Based on the correlation of package level and in-lab test results, a design process based on CDM target definition and device optimization, discharge path analysis, parasitic minimization, I/O data rate estimation and finally ESD and performance characterization is used sequentially to systematically realize the overall design goals.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Cao, Shuqing |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Dutton, Robert W |
| Primary advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Dutton, Robert W |
| Thesis advisor | Nishi, Yoshio, 1940- |
| Thesis advisor | Saraswat, Krishna |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Cao Shuqing. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Cao Shuqing
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