Nanoelectronics : technology assessment and projection at the device, circuit, and system level
Abstract/Contents
- Abstract
- Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are having diminishing return. Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system. The best devices are those that are optimized for the circuits and systems of the target application. Device design and engineering must aim at improvement at circuit and system level, while the new applications in various areas, such as life-science, are enabled by emerging technology. In this dissertation, the design space is explored for future Si CMOS technology, and several promising technologies in the post-Si era. Compact models of transport properties and capacitive components of different device structures have been developed to facilitate circuit-level analysis and system-level optimization. Possible ways of extending technology roadmap are proposed. We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits. Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI with the same power constraints at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates and 5MB SRAM per core. A new simple device technology assessment methodology based on energy-delay optimization is also introduced and applied on emerging devices including CNFETs, III-V field effect transistors (IIIV), and tunneling field effect transistors (TFET). In conclusion, this thesis addresses the significance of a holistic view across the traditional boundaries of device, circuit, and system in technology assessment and projection. Guided by this concept, we chart a new path for Si CMOS technology scaling for future technology generations. We also accomplish for the first time chip-level performance assessment and optimization of new emerging transistors such as CNFETs. This establishes a new benchmark and design methodology for emerging nanoelectronics.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2010 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Wei, Lan |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Saraswat, Krishna |
| Advisor | Mitra, Subhasish |
| Advisor | Saraswat, Krishna |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Lan Wei. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2010. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Lan Wei
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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