Transformer array power combining and stacking for CMOS RF power amplifiers
Abstract/Contents
- Abstract
- CMOS technology scaling has enabled the integration of RF transceivers on a single chip for various applications. However, as the feature sizes of the transistors scale, their breakdown voltages are reduced. Lower breakdown voltages lower the maximum voltage swings across the transistors and necessitate operation from a lower supply voltage. These factors, in turn, impose significant limitations on RF power amplifier design: (1) the low voltage swings limit the maximum power that can be delivered to the load, and (2) the DC-DC converter needed to generate a low supply voltage for the power amplifier from typical battery voltages increases the power consumption, size, and cost of the design. To address the first challenge, transistor stacking and transformer-based power combining are investigated as means of increasing the output power, while to address the second issue, transistor stacking and amplifier stacking are considered. Two CMOS RF power amplifier architectures serve as vehicles for exploring these concepts, each leading to the design and implementation of an experimental prototype. The first design is based on a stacked amplifier architecture with an off-chip matching network. Transistor stacking is used to increase the output power and supply voltage of the power amplifier, and a bias circuit is designed to enable operation of the power amplifier from a large supply voltage without exceeding the transistor breakdown limitations. The second design is an array RF PA architecture that employs (1) series-parallel transformers, (2) transistor stacking, and (3) amplifier stacking. This array RF PA uses series-parallel combinations of transformers to provide simultaneous impedance transformation and power combining. The proposed scalable transformer array architecture offers the possibility of designing a power amplifier to meet given specifications of output power and load impedance over a wide bandwidth. Stacking transistors in the array RF PA increases the output power provided by each of the unit PA stages comprising the array. In addition, the PA stages are themselves stacked. The two stacking methods increase the operating supply voltage. To demonstrate the proposed concept, a 2-by-4 amplifier array has been integrated in a 65-nm CMOS technology.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2013 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Fatḥī, Maryam |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Lee, Thomas |
| Primary advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Lee, Thomas |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Su, David (David Kuochieh) |
| Advisor | Su, David (David Kuochieh) |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Maryam Fathi. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2013 by Maryam Fathi
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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