Miniaturized, high-frequency DC-DC power conversion for embedded applications
Abstract/Contents
- Abstract
- In order to achieve high power density in battery-powered systems, as well as accommodate the reduced breakdown voltages in scaled CMOS technologies, systems-on-a-chip (SoCs) typically employ one or more supply voltages generated using dc-dc converters. Dc-dc converters are commonly implemented as inductive switching converters because of their high efficiency. However, inductive converters typically have a large footprint that is dominated by the size of bulky off-chip inductors and capacitors. In order to reduce the size of an inductive converter, its switching frequency can be increased by orders of magnitude above the existing practice. However, the use of a high switching frequency leads to increased switching power losses that in turn decrease the power conversion efficiency. To address this challenge, techniques for designing a high-efficiency buck converter while using miniaturized external components are investigated in this research. Design techniques, such as using a high switching frequency that is tunable with the load current and the segmentation and cascoding of power transistors are employed to achieve high power efficiency across a wide range of load currents. While in SoC applications multiple voltages are typically derived from battery by connecting converters in parallel, this work introduces a cascaded, dual-output buck converter topology. Cascading buck converters reduces the input supply voltage of the second converter, thus reducing the switching and ripple-conduction losses that severely affect the efficiency of buck converters using small inductors and operating at high switching frequencies. The use of high-frequency, cascaded conversion presents two significant challenges to the design of the controller for a buck converter. First is the need for adjustability of the switching frequency with varying load currents, and second is the possibility of cross regulation between the outputs of the converter. A digital constant-off-time controller is proposed to address these challenges. The controller enables tuning of the converter's switching frequency. The controller has a fast transient response and good line regulation that help to suppress cross regulation between the two outputs of the buck converter. To demonstrate the proposed multiple-output, cascaded, high-frequency converter, an experimental prototype has been integrated in a 90-nm CMOS technology. This prototype provides two output voltages using a cascade of two buck converters, each employing a small output capacitor on the order of 100 picofarads and a small inductor on the order of nanohenries, thereby reducing the overall size of the converter compared to conventional alternatives.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2013 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Arora, Sakshi |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Arbabian, Amin |
| Primary advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Su, David |
| Advisor | Su, David |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Sakshi Arora. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2013 by Sakshi Arora
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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