Nanoelectromechanical relays for low power digital systems
Abstract/Contents
- Abstract
- Since the invention of the integrated circuit in the late 1950s, complementary-metal-oxide-semiconductor (CMOS) scaling has made microelectronics ubiquitous in our daily lives. As CMOS circuits scale, the leakage current increases exponentially. The subthreshold slope of a MOSFET is theoretically limited to 60 mV/decade. Nanoelectromechanical (NEM) relays offer an alternative switching mechanism that enables nearly zero off state leakage current and sharp switching characteristics. The NEM relays, however, have much longer switching times compared to CMOS transistors. Due to the increasing complexity of scaling, producing application specific integrated circuits (ASICs) has become cost prohibitive for all but the highest volume applications. To provide a cost effective means of accessing advanced technology nodes, flexible digital circuits also known as field programmable gate arrays (FPGAs) are becoming more popular for a wide variety of applications. A digital function implemented on an FPGA, however, requires up to 35X more area and 14X more power while operating at a lower speed compared to the same function built on an ASIC. By incorporating NEM relays and CMOS transistors together, the low leakage characteristics of the NEM relay can be combined with the fast switching speeds of CMOS transistors. In the first part of this work, we review recent efforts to fabricate NEM relays and efforts to utilize NEM relays to improve the performance of FPGAs. We investigate the use of NEM relays as configurable, routing switches that can replace both the CMOS pass transistors and the accompanying SRAM cell. By following this method and by selectively resizing and removing routing buffers, the hybrid CMOS-NEM relay FPGA can achieve a 2X, 2X, and 10X improvement in area, dynamic power, and leakage power, respectively, compared to a CMOS-only FPGA. Realizing these benefits requires NEM relays with sub-10 kOhm on resistance that can be fabricated with back-end-of-line (BEOL) compatible processes. The NEM relays must also have a sufficiently large hysteresis window and actuation voltages with tight distributions to satisfy the half-select programming requirements. In the second part of this work, we design and fabricate NEM relays to meet these metrics. Novel lateral relays with decoupled electrode regions and compliant contacts are demonstrated. Arrays of these relays are demonstrated with over 90% of the devices meeting the resistance requirement and over 90% of the devices meeting the programming requirements. Most of these devices are fabricated with polysilicon and titanium nitride as the structural layer and contact material, respectively. SiGe is investigated as an alternative, BEOL compatible structural layer. Hafnium diboride and ruthenium are explored as alternative contact materials; on-resistances as low as 1.4 kOhm and 1.2 kOhm, respectively, are demonstrated. Outside of hybrid applications that combine CMOS and NEM relays on the same circuit, NEM relay circuits have been proposed as a means of performing very low energy digital logic. In the third part of this work, we develop the six-terminal relay, explore its use as a digital logic element, and demonstrate a NEM relay inverter.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2013 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Lee, William Scott |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Howe, Roger Thomas |
| Thesis advisor | Howe, Roger Thomas |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Mitra, Subhasish |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Wm [William] Scott Lee. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2013. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2013 by William Scott Lee
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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