Enabling "more than Moore" with graphene electronics : interconnects, devices, and circuits
Abstract/Contents
- Abstract
- Since the isolation of graphene in 2004, researchers have sought to exploit its unique electrical, thermal, and mechanical properties to extend "Moore's Law". However, most attempts have focused on conventional digital or analog applications. In this dissertation, I describe several technologies tailored to the unique properties of graphene that may enable greater performance unattainable with only "Moore's Law" scaling. First, I explore active graphene electronics in "beyond Moore" applications and describe a process to improve the quality and yield of graphene field-effect transistors via yttrium (Y) sacrificial layers. The Y sacrificial processing improves yield (from 73% to 97%), average device performance (3x mobility, 58% lower contact resistance), and device-to-device variability. Then, I explore wafer-scale graphene circuits for dot-product computation (GDOT), an essential kernel for emerging image processing and neural net applications. The GDOT utilizes high mobility GFETs to lower branch resistances, resulting in more effective low-pass filtering and enabling a higher effective number of bits (ENOB) over silicon CMOS-based implementations. Experimental, simulation, and mathematical analyses provide insight on device to circuit optimizations—specifically on the tradeoffs between device on/off ratio, output ripple, dot-product convergence accuracy, and power. Finally, I assess the capability of graphene in a passive electronic application: as an interconnect in very large scale integrated (VLSI) digital circuits, where the increasing resistivity of conventional copper wires restrict performance. Benchmarking in the context of a future 7-nm FinFET technology at several levels of abstraction (from standard cell to 32-bit commercial processor) elucidates VLSI design considerations. Full-core energy-delay-product (EDP) projections show ~8% improvement with graphene over copper interconnects. However, benefits could be larger through further design-technology co-optimization (DTCO) at the core level.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Wang, Ning Charles |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Murmann, Boris |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Ning Charles Wang. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2018. |
| Location | https://purl.stanford.edu/kr087wd1230 |
Access conditions
- Copyright
- © 2018 by Ning Wang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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