Low-voltage, low-power, high-resolution, broadband oversampling analog-to-digital conversion
Abstract/Contents
- Abstract
- Oversampling A/D converters exchange resolution in time for that in amplitude by oversampling the input signal and employing sigma-delta modulators that suppress quantization error within the signal bandwidth. As a result, a high-precision A/D converter output can be generated by using back-end digital decimation filtering. However, the use of oversampling converters is typically limited to low bandwidth applications, such as digital audio systems. Recently, sigma-delta modulators operating at relatively low oversampling ratios have been shown to be effective at achieving high-performance A/D conversion for signal bandwidths of several megahertz. However, the limited signal swings and voltage headroom that accompany the aggressive scaling of CMOS technology result in high power dissipation of the analog circuits in conventional modulator architectures. Although sigma-delta modulators based on input feedforward architectures enable reduced analog power dissipation, they require a high-speed quantizer and feedback DAC with attendant high power dissipation. The objective of this research is to investigate means of power minimization for both analog and digital circuits in sigma-delta modulators operating from low supply voltages over several mega-hertz of signal bandwidth while maintaining high precision. To relax the timing constraints on the quantizer and feedback DAC, a half-sample delayed-input feedback architecture is employed in the implementation of a second-order sigma-delta modulator. Power dissipation in the analog amplifiers of the feedforward architecture is reduced by using a single amplifier to implement the two integrators. This amplifier sharing also reduces the area occupied by the integrators. The power scaling of amplifiers in discrete-time multi-order amplifier-based analog integrators is exploited by dynamically biasing the shared amplifier. A low-power, high-speed charge pump circuit for dynamic biasing minimizes the power overhead. Finally, a multi-bit quantizer, which effectively reduces the output amplitude and power dissipation of the integrators, employs interpolated preamplifiers to conserve power and area in the preamplifiers. A 2-2 cascaded sigma-delta modulator, operating from a 1.0-V supply, has been designed using a half-sample delayed-input feedforward architecture for each stage, dynamically-biased amplifier sharing for realization of the integrators, and interpolated multi-bit quantization. An experimental prototype of the proposed modulator has been integrated in a 0.18-[micrometer] CMOS technology. At a 40-MHz sampling rate, the prototype achieves 92 dB of dynamic range, a 91-dB peak SNR and an 84-dB peak SNDR for a signal bandwidth of 1.25 MHz, while consuming only 24.3 mW of total power from a 1.0-V supply.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Cho, Je-Kwang |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Thesis advisor | Dutton, Robert W |
| Thesis advisor | Murmann, Boris |
| Advisor | Dutton, Robert W |
| Advisor | Murmann, Boris |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Je-Kwang Cho. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Je-Kwang Cho
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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