Nonvolatile monolithic three-dimensional field programmable gate array with stacked resistive configuration memory
Abstract/Contents
- Abstract
- The majority of conventional Field Programmable Gate Arrays (FPGAs) store their configuration bits in Static Random Access Memory (SRAM) on chip. Configuration SRAM is the primary contributor to the large area, power consumption and delay of FPGAs relative to Application Specific Integrated Circuits (ASICs). The solution is a Three-Dimensional (3D) FPGA, in which the configuration memory is vertically stacked over programmable logic and routing fabric. Several 3D-FPGA concepts with various integration schemes and alternative memory technologies for the configuration memory have been demonstrated recently. However, those concepts required materials and process that may not be compatible or scalable with standard CMOS process. This dissertation presents the first experimental 3D-FPGA with monolithically stacked configuration memory based on the emerging Resistive Random Access Memory (RRAM) technology, which is compatible and scalable with CMOS process. The RRAM, here, are not used in a typical FLASH memory application. Rather, they are used as programmable resistors to construct configuration memory cells that store and represent active static logic. To demonstrate the concept, a 1Kbit nonvolatile resistive configuration memory array and a 17x17-tile 3D-FPGA with 21Kbit configuration are fabricated and tested. This dissertation delves into the architecture, design, implementation, fabrication and validation of the memory array and 3D-FPGA prototypes. Both prototypes are implemented in 0.18um general purpose CMOS process with 1 poly-silicon and 6 metal layers. The programmable resistors (RRAM) are sandwiched between the 5th and 6th metal layers. The measurement results demonstrated the concept of resistive configuration memory and confirmed the programmability and logic functionality of the RRAM based 3D-FPGA. This dissertation also projects the potential improvements in area, energy consumption and delay of the RRAM based 3D-FPGA over conventional SRAM based design, when the prototype is scaled to advanced 65nm CMOS technology. Simulation result shows 40% reduction in area is expected. This work also examines the potential benefits of monolithic 3-layer 3D-FPGA, designed also in the 65nm node. Simulation results show that 70% area reduction is expected.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2012 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Yang Liauw, Young Feng |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Wong, S. Simon |
| Thesis advisor | Wong, S. Simon |
| Thesis advisor | El Gamal, Abbas A |
| Thesis advisor | Pease, R. (R. Fabian W.) |
| Advisor | El Gamal, Abbas A |
| Advisor | Pease, R. (R. Fabian W.) |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Young Feng Yang Liauw. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2012. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2012 by Young Feng Yang Liauw
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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