Design technology co-optimization of energy-efficient digital logic using carbon nanotubes
Abstract/Contents
- Abstract
- Carbon nanotube (CNT) field-effects transistors (FETs) are promising candidates for high-speed and low-energy digital logic. CNT FETs have been integrated within multiple industrial fabrication facilities at mature technology nodes (e.g., 90/130nm on 200mm silicon wafers). However, understanding CNT energy and delay benefits at extremely scaled nodes (e.g., beyond 2nm) is difficult due to several reasons: 1. CNT FETs have distinct characteristics -- material properties and fabrication techniques -- versus silicon FETs, that directly impact digital logic energy and delay. 2. CNT FET energy efficiency analysis must include CNT FET minimum leakage current. 3. CNT FET digital logic energy and delay exhibit numerous trade-offs, far beyond those for silicon FETs. I address these challenges through new physics-based models using physically meaningful parameters, new CNT FET doping and layout design techniques, and extensive Design Technology Co-Optimization (DTCO). To illustrate new physics-based models, I present the extended scale length theory. It captures the differences between CNT FET and silicon FET electrostatics that are crucial for energy and delay estimation. It is used to quantify CNT FET minimum leakage current within 3× vs. experimentally calibrated Non-Equilibrium Green's Function (NEGF) solvers. In contrast, prior models can underestimate CNFET minimum leakage current by 105×. Understanding CNT FET digital logic energy and delay trade-offs requires extensive DTCO simulations across many design and technology parameters. My new physics-based models enable fast DTCO: over 350,000 simulations in a few days vs. several months using existing Technology CAD simulators. Such extensive DTCO helps derive CNT FET design and technology parameters with up to 7× projected Energy-Delay Product (EDP) benefits vs. silicon FETs at the 2nm technology node. These DTCO simulations also include a new CNT FET extension doping technique based on the concept of a barrier booster. A new logic layout technique called Omni 3D exploits CNFET low-temperature fabrication to further enable up to 1.9× additional projected EDP benefits. Several of my thesis contributions extend beyond CNT FETs, e.g., to FETs based on two-dimensional materials.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2024; ©2024 |
| Publication date | 2024; 2024 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Gilardi, Carlo |
|---|---|
| Degree supervisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Pop, Eric |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, School of Engineering |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Carlo Gilardi. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2024. |
| Location | https://purl.stanford.edu/jq719cs3351 |
Access conditions
- Copyright
- © 2024 by Carlo Gilardi
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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