On-chip buck-boost switched-capacitor DC-DC converter
Abstract/Contents
- Abstract
- The increasing integration level of CMOS integrated circuits (ICs) poses significant challenges for the power delivery network. Multiple independent power domains, each of them individually adjustable, are desirable for complex ICs to optimize the tradeoff between performance and energy consumption. A two-stage power management system, in which a first-stage global converter with a large down conversion ratio is followed by multiple second-stage local regulators for different power domains, fits well in modern power delivery networks. The first stage can be built with conventional, fully optimized DC-DC converters, while the second stage requires flexible, high-density, and high-efficiency on-chip DC-DC converters. With the enhanced fabrication capability of high-density on-chip capacitors, the switched-capacitor (SC) DC-DC converter becomes a perfect candidate for these second-stage on-chip regulators. This dissertation presents the architecture, modeling and design techniques for the development of fully integrated on-chip SC DC-DC converters for the purpose of local regulation. The proposed converter can step up or down the voltage based on the output requirement and circuit performance. Using the unit cell array approach, conversion ratios of n/(n+1) with buck configurations and (n+1)/n with boost configurations are achievable when n cells are grouped as a single converter. Thus, adequate topologies exist to provide a large range of output voltage with high efficiency. A prototype chip with 204 unit cells and nine different finely spaced buck and boost topologies was designed and fabricated in a 45nm bulk CMOS technology. The input is 1V, and the output ranges from 0.58V to 1.3V. The SC converter achieves a peak efficiency of 82.2% at a maximum power density of 0.16W/mm2. Furthermore, the efficiency varies by only 4.2% over the output voltage range. A digital algorithm for closed loop control was implemented in a field-programmable gate array (FPGA) to demonstrate that performance regulation using this type of converter can match circuit performance requirements and compensate for operating conditions or process variations. This dissertation also projects the potential improvements in SC converters with more advanced technology nodes as well as capacitor density scaling, such as using special on-chip capacitor processes like Metal-Insulator-Metal (MIM) capacitors and deep trench capacitors.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Wang, Chaohao |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Wong, S. Simon |
| Thesis advisor | Wong, S. Simon |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Murmann, Boris |
| Advisor | Arbabian, Amin |
| Advisor | Murmann, Boris |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Chaohao Wang. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Chaohao Wang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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