Engineering novel chalcogenides and semimetals for energy-efficient memory and interconnects
Abstract/Contents
- Abstract
- Today's nanoelectronics systems are approaching fundamental limits of energy and latency for numerous data-intensive Internet of Things devices and artificial intelligence applications. To tackle this challenge, future electronics (whether flexible, 3D, neuro-inspired or not) will require energy-efficiency in computing, data-storage, and their interconnections. This calls for the adoption of new materials and for bridging the advances in their transport physics, electronic devices, and systems to enable breakthroughs in low-power memory and interconnects. In this thesis, I present atomic-scale materials engineering to demonstrate several key advances in nanoscale memory and interconnects. First, I demonstrate how electro-thermal control using atomically thin chalcogenides and their superlattices can enable energy-efficient neuro-inspired phase-change memory for both rigid and flexible electronics, unlike existing data storage technology. I explain how engineering the chalcogenide and superlattice materials properties leads to improved memory device performance and tunability, crucial for robustness and optimization. These efforts have led to the lowest programming current density of 0.1 MA/cm2 to-date, and one of the first reports of sub-1 V switching in phase-change memory technology. Next, I introduce an unconventional resistivity scaling (i.e., resistivity decreases in thinner films, unlike conventional metals) in ultrathin transition metal mono-phosphides NbP and TaP. I further probed the surface-state-dominated conduction in thin films of these semimetals that give rise to such unconventional scaling trends. This could open a new paradigm for ultrathin interconnects, going beyond the metal-resistance bottleneck in traditional metals like copper. Together, these results illustrate how combining versatile material functionalities and probing their transport fundamentals can unlock decade-spanning advances in heterogeneously integrated nanoelectronics.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2023; ©2023 |
| Publication date | 2023; 2023 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Khan, Asir Intisar |
|---|---|
| Degree supervisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, H.S.Philip |
| Degree committee member | Saraswat, Krishna |
| Degree committee member | Wong, H.S.Philip |
| Associated with | Stanford University, School of Engineering |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Asir Intisar Khan. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2023. |
| Location | https://purl.stanford.edu/jm859kh0212 |
Access conditions
- Copyright
- © 2023 by Asir Intisar Khan
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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