Improving contacts and doping to two-dimensional transition metal dichalcogenides
Abstract/Contents
- Abstract
- Silicon technology has driven the technological evolution of modern society through the Moore's law since the 1960s. The continued scaling of silicon transistors has driven down the cost per transistor while increasing the performance and power efficiency of our computing devices. The personal and mobile computing revolution of the last two decades is a testament to this. However, the scaling of silicon transistors is slowing down as we are reaching the limits of silicon and other conventional semiconductors like germanium and III-Vs in both performance and power efficiency. The future of Moore's law may lie in scaling in the third dimension by stacking transistors vertically. Three-dimensional monolithic integration of transistors has been proposed to continue the Moore's law by driving down the cost per transistor while improving the performance and power-efficiency by cutting down on interconnect power dissipation and delay. However, Si is not compatible with the back-end-of-line (BEOL) thermal constraints because it requires high temperature processing steps. Two-dimensional (2D) Transition Metal Dichalcogenides (TMDs) can be processed at much lower BEOL-compatible temperatures without sacrificing performance. 2D TMDs are also promising for nanoscale transistor applications because they retain excellent mobility even in the monolayer form with sub-1 nm thickness unlike conventional Si. However, the parasitic contact resistance is a huge problem in 2D TMDs that limits their electrical performance. First, we develop a nanofabrication and electrical characterization platform for robust testing of metal contacts to monolayer (1L) MoS2, a 2D TMD that is less than 7 Å thick. We perform reproducible analysis of contacts that is enabled by atomic-layer deposited encapsulation layer and statistical analysis of 432 transistors. These devices are modeled using Technology Computer-Aided Design (TCAD) to understand the non-idealities and intricacies in the analysis of contacts. Next, using this analysis platform, we develop and optimize a low-resistance contact technology which uses alloys of the low melting point metals In and Sn. Further, we show that alloying can be used to improve the temperature tolerance of these metal contacts up to 450 ºC to make them back-end processing compatible and manufacturing friendly. We demonstrate a record low contact resistance to 1L MoS2 of 190 Ω·µm, which is the lowest reported contact resistance that is compatible with back-end processing. Doping of 2D TMDs is also essential to mitigate the large contact resistance in the top-gated transistor configuration. We demonstrate the n-type doping of bilayer WS2 transistors using the atomic layer deposited (ALD) sub-stoichiometric aluminum oxide (AlOx) doping layer. To understand the origin of the doping effect, we model the WS2/Al2O3 interface using density functional theory (DFT) calculations which reveals that the n-type doping is caused by Al-termination and oxygen vacancies in the Al2O3 layer. These vacancies act as electron donors and induce remote charge-transfer doping into the WS2 channel. We studied the degradation in transistor performance and effectiveness of n-type doping over 21 months and make suggestions to improve the stability of this doping technique. This work provides a path towards ultralow resistance contact electrodes to 2D TMDs while maintaining compatibility with Si processing and back-end-of-line thermal budget.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2022; ©2022 |
| Publication date | 2022; 2022 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Kumar, Aravindh |
|---|---|
| Degree supervisor | Saraswat, Krishna |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Pop, Eric |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Aravindh Kumar. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2022. |
| Location | https://purl.stanford.edu/jh125rt4498 |
Access conditions
- Copyright
- © 2022 by Aravindh Kumar
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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