Monolithic three-dimensional integration of III-V compound semiconductors on silicon
Abstract/Contents
- Abstract
- The planar scaling of silicon-based electronics technology has become much more challenging. Stacking devices in the vertical direction provides possible better performance and higher device density. Integrating different electronic or even optical components on top of silicon integrated circuits (ICs) can realize multi-functional ICs or ultimately, a system-on-chip. III-V semiconductor compounds have been used in optoelectronics and are also promising candidates for alternative channel materials in the next generation complementary-metal-oxide-semiconductor (CMOS) technology. Hetero-integration of high quality III-V single crystals on top of Si ICs will enable a wide variety of applications. However, there are three major challenges in building monolithic 3-dimensional integration circuits (3DICs): obtaining single crystalline device-grade semiconductor films; transfer of these films on to prefabricated silicon wafers; and fabricating devices that are compatible with existing structures in the silicon wafer. A possible experimental solution is to use the rapid-melt-growth (RMG) method to prepare single crystalline materials on silicon, which could solve the first two challenges together. In the first part of this dissertation, a modified RMG process is proposed and examined specifically for GaSb and InAs growth on silicon in order to solve the low III-V single crystalline yield problem using the conventional RMG method. Several possible causes of the low yields in the process design and conditions are identified, and experimental solutions are given. The geometry dependence of the RMG structure and the scaling potential are also discussed. III-V MOSFETs using the RMG-grown GaSb and InAs crystals are then fabricated to demonstrate the viability of 3DIC hetero-integration, under low thermal-budget (< 400oC) constraints. The second issue discussed in this work is using the wafer bonding method to realize monolithic 3D integration. Comparisons between wafer bonding and the RMG approach are made.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2017 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Chen, Chien-Yu |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Griffin, Peter |
| Primary advisor | Plummer, James D |
| Thesis advisor | Griffin, Peter |
| Thesis advisor | Plummer, James D |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, S |
| Advisor | Saraswat, Krishna |
| Advisor | Wong, S |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Chien-Yu Chen. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2017. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2017 by Chien-Yu Chen
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
Also listed in
Loading usage metrics...