Design of high-speed, high-resolution SAR A/D converters in nano-scale CMOS processes
Abstract/Contents
- Abstract
- This research investigates the design of high-speed SAR ADCs to identify circuit techniques that improve their conversion speed while maintaining low energy operation. In addition, it explores the limitations of pipelined-SAR ADCs, which recently have demonstrated high power efficiency at conversion rates of several tens of MS/s and SNDR > 65 dB. A modified pipelined-SAR architecture is proposed, which uses two switched-capacitor digital-to-analog converters (DACs) at the ADC frontend. This technique separates the high-speed SAR operation from the low noise residue computation and improves the conversion speed to over 150 MS/s while maintaining an SNDR > 65 dB with good power efficiency. Three prototype ICs were designed during this work. First, a test structure to extract mismatch information of small (~1fF) on-chip single-metal MOM capacitors was designed in the IBM 32 nm SOI CMOS process. Measurement results show very good matching characteristics with a matching coefficient of approximately 0.85%×1fF. Next, an 8-bit SAR ADC was designed in a 65 nm CMOS process. This design uses 0.75 fF unit capacitors in the DAC, top-plate sampling with symmetric DAC switching, SAR loop delay optimization, and a fast comparator optimized for regeneration and reset. Measured results show an SNDR of 47.3 dB (Nyquist input) at 450 MS/s with a Walden FOM of 72 fJ/conv-step. Lastly, to evaluate the proposed pipelined-SAR architecture, a prototype ADC was implemented in a 65 nm CMOS process. Measured results show an SNDR of 68.3/66 dB at low frequency/Nyquist inputs, respectively with a sampling frequency of 160 MS/s, which corresponds to a Schreier FOM of 167/164.7 dB respectively. These results validate the concept of the proposed two switched-capacitor DAC pipelined-SAR architecture, and the achieved performance compares favorably with the state of the art.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2014 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Tripathi, Vaibhav |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Murmann, Boris |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Advisor | Arbabian, Amin |
| Advisor | Wooley, Bruce A, 1943- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Vaibhav Tripathi. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2014. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2014 by Vaibhav Tripathi
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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