System-driven circuit design for ADC-based wireline data links
Abstract/Contents
- Abstract
- In the era of connectivity, wireline I/O has been a key technology underpinning the aggressive performance improvements of computer and communication systems. All standards, ranging from electrical to optical, long haul to short reach interconnects, have increased their aggregate bandwidth at a rate of about 2x every 4 years. This trend drives the usage of multi-level modulation schemes, such as PAM4. As a result, ADC-DSP based links are gaining more attention and are now heavily investigated. ADC links also take advantage of the intrinsic bandwidth and area improvements from process technology scaling. It is becoming very difficult for conventional mixed-signal links to meet the bandwidth and performance requirements of next-gen systems. As equalization is moved into the digital domain for ADC-based links, the ADC needs to be very fast, have reasonably high resolution and yet be very power efficient. Consequently, these stringent requirements pose significant challenges in both ADC links' architecture and circuit design. In this thesis, we focus on a statistical framework for understanding ADC nonidealities, including quantization and nonlinearity, and their impact in a link context. We will then present studies on equalization locations along the link's signal path, motivating the need of pre-equalization before the ADC. With the importance as well as the implementation challenges of pre-equalizers in mind, we present the first inverterbased analog front-end (AFE) for 56Gb/s transceivers for both PAM2 and PAM4 vapplications. Such AFEs include continuous time linear equalizers (CTLE), programmable gain amplifiers (PGA) and the ADC's track and hold circuits (T/H). The inverter-based AFE is process scaling friendly, consumes smaller power and achieves significant area reduction over prior art. Finally, system identification (SID) methodologies are used with silicon measurements to show validity of the before-mentioned analysis. SID-based bit error rate (BER) estimation method is also presented to compare measured and predicted link performance for different ADC resolutions.
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource. |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2018; ©2018 |
| Publication date | 2018; 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Zheng, Kevin |
|---|---|
| Degree supervisor | Murmann, Boris |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Arbabian, Amin |
| Thesis advisor | Horowitz, Mark (Mark Alan) |
| Degree committee member | Arbabian, Amin |
| Degree committee member | Horowitz, Mark (Mark Alan) |
| Associated with | Stanford University, Department of Electrical Engineering. |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Kevin Zheng. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis Ph.D. Stanford University 2018. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2018 by Kevin Jie Zheng
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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