Approaching the limits of contact resistance and scaling in molybdenum disulfide transistors
Abstract/Contents
- Abstract
- For half a century, decreasing transistor dimensions (following Moore's Law) have increased the performance and lowered the cost of computer electronics. Today's transistors have nanoscale features, but the ultimate limit is the atomic scale with sub-nanometer thin channels, which are not feasible with conventional semiconductors such as silicon. Monolayer semiconductors like MoS2 are intrinsically only three atoms thick, and thus have exciting potential for use in future atomic-scale electronics. This work explores the fundamental performance limits of MoS2 transistors in the context of transistor scaling. First, I discuss the contact resistance, which is a key factor limiting the performance of short channel devices. A systematic study of contacts to MoS2 with varying metals and fabrication conditions reveals that gold deposited in ultra-high vacuum yields three times lower contact resistance (~740 Ω⋅μm) than under normal conditions. Using this technique, MoS2 transistors with contact lengths down to 20 nm are demonstrated. Modeling provides key insights on how to further improve the contacts to approach fundamental limits. Next, using a novel self-aligned fabrication technique, I demonstrate transistor gate lengths down to 10 nm. At this length scale, I provide the first analysis of ballistic transport in monolayer MoS2, which is the ultimate performance limit for these transistors. Quasi-ballistic behavior with transmission coefficient up to 0.25 at 175 K, and up to 0.15 at room temperature is demonstrated. I also project the intrinsic performance of MoS2 transistors, demonstrating the potential for applications in low-power electronics. With the same technique, I also fabricate double gate transistors to examine the scaling limits of monolayer MoS2. These devices reach high saturation current > 500 μA/μm and transconductance > 200 μS/μm, a record for any sub-nanometer thin semiconductor, and comparable to modern silicon-on-insulator technology. Simulations examine how such devices can be further scaled down, finding that thinning the gate oxide is crucial once the channel has reached few-atom thickness. In the last chapter I use mm-wide devices to measure monolayer MoS2 transistor leakage currents down to 60 aA/μm and current on/off ratios greater than 10^11, both records for this material. Overall, these results demonstrate that MoS2 can bring transistor technology to the ultimate atomic-scale limit.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2017 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | English, Christopher David |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Saraswat, Krishna |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Christopher David English. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2017. |
| Location | https://purl.stanford.edu/hs748bt7446 |
Access conditions
- Copyright
- © 2017 by Christopher David English
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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