Energy-efficient digital VLSI using carbon nanotube field-effect transistors
Abstract/Contents
- Abstract
- Carbon Nanotube Field-Effect Transistors (CNFETs) are a promising emerging nanotechnology for improving the energy efficiency (quantified by the energy-delay product, EDP) of digital very large-scale integrated (VLSI) circuits. However, the benefits of realistic CNFET digital VLSI circuits at sub-10 nm technology nodes aren't well understood. I begin by quantifying the digital VLSI circuit-level EDP benefits of CNFETs vs. alternative technologies currently under consideration (e.g., progressing from today's FinFETs to nanowires) at the 7 nm and 5 nm technology nodes. I show that CNFETs can enable digital VLSI logic circuits to run 3× faster, while simultaneously consuming 3× less energy, resulting in 9× EDP benefit. This analysis also provides insights into the sources of these benefits. Despite their projected benefits, CNFETs are subject to variations inherent to carbon nanotubes (CNTs): variations in CNT type (semiconducting or metallic), CNT density or CNT diameter, to name a few. Such variations can lead to near-zero functional yield, increase susceptibility to noise, or degrade EDP benefits of CNFET digital circuits. To overcome CNT variations, joint exploration and optimization of CNT processing parameters (to be improved during CNFET fabrication) and CNFET digital circuit design are required. Existing approaches for such exploration and optimization rely on trial-and-error-based ad hoc techniques resulting in very long computation runtimes. I present a new approach that achieves fast runtimes (e.g., 30 minutes for a processor core design vs. a month using existing approaches). I use this approach to derive multiple design points (each representing a combination of parameters for CNT processing and CNFET circuit design) to overcome CNT variations. These design points preserve 90% of the projected EDP benefits of CNFET digital circuits (despite CNT variations), while simultaneously meeting circuit-level yield and noise margin constraints. The derived design points directly influence experimental research on CNFETs. While co-optimized CNT processing and CNFET circuit design can overcome CNT variations, the required CNT processing advances have not yet been achieved. Alternatively, I present a design approach that can deliver EDP benefits of CNFET digital circuits despite CNT variations that exist in today's CNFET fabrication -- without requiring further CNT processing improvements to overcome CNT variations. This new design technique, Technique for Reducing errors using Iterative Gray code (TRIG), is applicable for inference-based applications that rely on serial matrix operations (serial: accumulated over at least 2 clock cycles) to draw conclusions, such as classification, from analyzing large amounts of data. As a case study, I analyze the effectiveness of TRIG for a hardware accelerator targeting image classification. Despite CNT variations that exist today, TRIG can maintain 99% (90%) of projected EDP benefits of CNFET digital circuits for 90% (99%) image classification accuracy target.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Publication date | 2018 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Hills, Gage |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering. |
| Primary advisor | Mitra, Subhasish |
| Thesis advisor | Mitra, Subhasish |
| Thesis advisor | Murmann, Boris |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Advisor | Murmann, Boris |
| Advisor | Wong, Hon-Sum Philip, 1959- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Gage Hills. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Thesis (Ph.D.)--Stanford University, 2018. |
| Location | electronic resource |
Access conditions
- Copyright
- © 2018 by Gage Krieger Hills
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