Nanoscale electrical and thermal interfaces to resistive memory devices
Abstract/Contents
- Abstract
- Future computing systems need ultra-high storage densities for large volumes of data. Non-volatile resistive random-access memory (RRAM) based on metal oxides or phase-change materials could enable such high capacity with low latency. However, as memory cell dimensions are reduced to sub-10 nm scale, their contacts, interfaces, and self-heating can determine the memory device behavior and packing density, yet these are poorly understood. In the first half of my thesis, I will show that the electrical contact resistivity varies over 10 orders of magnitude depending on the memory material considered; cubic Ge2Sb2Te5 has contact resistivity near 10 mΩ⋅cm2 while contact resistivity to as-deposited HfO2 is as high as 0.5 MΩ⋅cm2, at room temperature. I will then showcase switching measurements on nanoscale memory devices and insights gleaned about the role of contact resistance. In the second half of my thesis, I will demonstrate some of the first nanoscale thermal measurements on resistive memory devices using scanning thermal microscopy. With a single-layer graphene as a top electrode, I show the most thermally intimate measurement of an RRAM filament to date and observe a device temperature rise > 300°C. Varying the thermal conductivity of electrodes over a 50x range, I investigate device-level heat spreading and conclude that Joule heating in a sub-10 nm filament can cause a temperature rise up to 200°C, even at a distance of 50 nm from a typical RRAM device. By comparison to simulations, I show that the filament itself can reach temperatures in excess of 1200°C within its hourglass-like sub-10 nm dimension geometry. This filament temperature strongly depends on the thermal boundary resistance at the filament-electrode interfaces. These novel insights point to the importance of nanoscale thermal engineering of the filament-electrode interfaces and of the electrodes to minimize array level thermal cross-talk and to enable ultra-high storage densities
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2020; ©2020 |
| Publication date | 2020; 2020 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Deshmukh, Sanchit Kiran |
|---|---|
| Degree supervisor | Pop, Eric |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Degree committee member | Saraswat, Krishna |
| Degree committee member | Wong, Hon-Sum Philip, 1959- |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Sanchit Kiran Deshmukh |
|---|---|
| Note | Submitted to the Department of Electrical Engineering |
| Thesis | Thesis Ph.D. Stanford University 2020 |
| Location | https://purl.stanford.edu/hf925rs7097 |
Access conditions
- Copyright
- © 2020 by Sanchit Kiran Deshmukh
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
Also listed in
Loading usage metrics...