High-voltage-tolerant I/O design for USB 2.0-compliant systems
Abstract/Contents
- Abstract
- The design of I/O user interfaces continues to grow in importance as the "digital revolution" gathers momentum. In such I/O interfaces, one frequently occurring challenge is the need to accommodate over-voltage conditions, in which the I/O signals range beyond the nominal voltage ratings of the I/O supplies. This vulnerability results from the fact that most I/O ports are exposed to users during operation, resulting in relatively uncontrolled terminations or even user abuse. This problem is exacerbated by a mismatch in the scaling rates of CMOS processes and I/O standards, forcing transistors with reduced voltage tolerance to implement interfaces with higher I/O voltages. The design problems associated with over-voltage conditions are important because it directly affects the lifetime of the product. In this work, we identify design challenges in the presence of over-voltage conditions and derive design guidelines for end-user systems taking a USB 2.0-compliant I/O as a test vehicle. We further demonstrate over-voltage-protected I/O circuits and high-robustness on-chip ESD protection in a 90-nm CMOS process. Our I/O circuit provides over-voltage protection against stress ranging from -1 to 5.25 V with continuous monitoring and compatibility with power-down mode. To enable this protection using today's CMOS technology, an additional bias voltage is used. Also, a dedicated over-voltage detection circuit with no static power consumption centrally controls protection paths to realize continuous monitoring. The protection concept of the I/O circuits integrated in the USB transmitters and receivers has been demonstrated with and without power present. Our ESD design realizes an extremely robust on-chip ESD protection concept, achieving an ESD robustness of 5 A TLP current, equivalent to an 8 kV HBM level, while fulfilling the over-voltage and high-speed requirements of the USB 2.0 system. The proposed architectures, employing SCR devices with triggering circuits implemented using a diode-string or a PMOS device, exhibit high ESD robustness, compatibility with over-voltage conditions, and suppressed interaction between the ESD circuit and regular I/O signaling in any state of system power.
Description
| Type of resource | text |
|---|---|
| Form | electronic; electronic resource; remote |
| Extent | 1 online resource. |
| Copyright date | 2010 |
| Publication date | 2009, c2010; 2009 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Associated with | Kim, Moon-Jung |
|---|---|
| Associated with | Stanford University, Department of Electrical Engineering |
| Primary advisor | Lee, Thomas |
| Thesis advisor | Lee, Thomas |
| Thesis advisor | Wong, S |
| Thesis advisor | Wooley, Bruce A, 1943- |
| Advisor | Wong, S |
| Advisor | Wooley, Bruce A, 1943- |
Subjects
| Genre | Theses |
|---|
Bibliographic information
| Statement of responsibility | Moon-Jung Kim. |
|---|---|
| Note | Submitted to the Department of Electrical Engineering. |
| Thesis | Ph.D. Stanford University 2010 |
| Location | electronic resource |
Access conditions
- Copyright
- © 2010 by Moon-Jung Kim
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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