Towards low temperature solid source synthesis of monolayer molybdenum disulfide and low resistance contacts to molybdenum disulfide-based devices
Abstract/Contents
- Abstract
- Silicon (Si) transistors have recently reached nanometer-scale dimensions. Further gate length scaling requires thinner body channels and low resistance contacts. Yet, Si carrier mobility severely degrades at thicknesses below ~3 nm due to surface roughness, leading to lower on-state current for short gate-length transistors. MoS2 is a 2-dimensional (2D) atomically smooth semiconductor that retains its band gap and electrical properties down to single monolayers (3 atoms thick), making it appealing for transistor gate length scaling. In addition, stacking of transistors in 3 dimensions (3D) will be needed to further increase their density when 2D scaling reaches diminishing return. However, synthesizing high mobility MoS2 with thin layers and low resistance contacts has been an ongoing challenge in developing MoS2 for such applications. In addition, for many 3D heterogeneous integration applications, relatively low temperature (400-600°C) material deposition techniques are necessary, on time scales of 2 hours or less. In the first part of this thesis, we describe the chemical vapor deposition (CVD) growth of MoS2 using solid source precursors. By carefully controlling precursor amount and placement as well as optimizing the temperature heating ramp, sulfur (S) injection is optimally timed for efficient reaction with molybdenum trioxide (MoO3). In the second part, we describe efforts to make low-resistance metal contacts to MoS2. By inserting a Ta2O5 insulator layer between metal contacts and multi-layer MoS2, contact resistance can be reduced by up to 3 orders of magnitude along with significant Schottky barrier height reduction. In the final part, we report electrical characteristics of 1L MoS2 grown at 560°C with carrier mobility comparable to 1L MoS2 grown at higher temperatures, within the 600°C thermal budget for back-end-of-line (BEOL) processing and 3D integration. The record high drive currents and effective mobilities achieved on these 560°C 1L films are the best reported for solid source CVD-grown 1L MoS2 below 600°C providing an encouraging path towards utilizing MoS2 to continue transistor density scaling into the future
Description
| Type of resource | text |
|---|---|
| Form | electronic resource; remote; computer; online resource |
| Extent | 1 online resource |
| Place | California |
| Place | [Stanford, California] |
| Publisher | [Stanford University] |
| Copyright date | 2021; ©2021 |
| Publication date | 2021; 2021 |
| Issuance | monographic |
| Language | English |
Creators/Contributors
| Author | Tang, Alvin Universe |
|---|---|
| Degree supervisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Wong, Hon-Sum Philip, 1959- |
| Thesis advisor | Pop, Eric |
| Thesis advisor | Saraswat, Krishna |
| Degree committee member | Pop, Eric |
| Degree committee member | Saraswat, Krishna |
| Associated with | Stanford University, Department of Electrical Engineering |
Subjects
| Genre | Theses |
|---|---|
| Genre | Text |
Bibliographic information
| Statement of responsibility | Alvin Universe Tang |
|---|---|
| Note | Submitted to the Department of Electrical Engineering |
| Thesis | Thesis Ph.D. Stanford University 2021 |
| Location | https://purl.stanford.edu/gr942qn0912 |
Access conditions
- Copyright
- © 2021 by Alvin Universe Tang
- License
- This work is licensed under a Creative Commons Attribution Non Commercial 3.0 Unported license (CC BY-NC).
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